Lionel Debieve | 65805c1 | 2019-09-25 15:03:59 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019, STMicroelectronics - All Rights Reserved |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef DRIVERS_SPI_NAND_H |
| 8 | #define DRIVERS_SPI_NAND_H |
| 9 | |
| 10 | #include <drivers/nand.h> |
| 11 | #include <drivers/spi_mem.h> |
| 12 | |
| 13 | #define SPI_NAND_OP_GET_FEATURE 0x0FU |
| 14 | #define SPI_NAND_OP_SET_FEATURE 0x1FU |
| 15 | #define SPI_NAND_OP_READ_ID 0x9FU |
| 16 | #define SPI_NAND_OP_LOAD_PAGE 0x13U |
| 17 | #define SPI_NAND_OP_RESET 0xFFU |
| 18 | #define SPI_NAND_OP_READ_FROM_CACHE 0x03U |
| 19 | #define SPI_NAND_OP_READ_FROM_CACHE_2X 0x3BU |
| 20 | #define SPI_NAND_OP_READ_FROM_CACHE_4X 0x6BU |
| 21 | |
| 22 | /* Configuration register */ |
| 23 | #define SPI_NAND_REG_CFG 0xB0U |
| 24 | #define SPI_NAND_CFG_ECC_EN BIT(4) |
| 25 | #define SPI_NAND_CFG_QE BIT(0) |
| 26 | |
| 27 | /* Status register */ |
| 28 | #define SPI_NAND_REG_STATUS 0xC0U |
| 29 | #define SPI_NAND_STATUS_BUSY BIT(0) |
| 30 | #define SPI_NAND_STATUS_ECC_UNCOR BIT(5) |
| 31 | |
| 32 | struct spinand_device { |
| 33 | struct nand_device *nand_dev; |
| 34 | struct spi_mem_op spi_read_cache_op; |
| 35 | uint8_t cfg_cache; /* Cached value of SPI NAND device register CFG */ |
| 36 | }; |
| 37 | |
| 38 | int spi_nand_init(unsigned long long *size, unsigned int *erase_size); |
| 39 | |
| 40 | /* |
| 41 | * Platform can implement this to override default SPI-NAND instance |
| 42 | * configuration. |
| 43 | * |
| 44 | * @device: target SPI-NAND instance. |
| 45 | * Return 0 on success, negative value otherwise. |
| 46 | */ |
| 47 | int plat_get_spi_nand_data(struct spinand_device *device); |
| 48 | |
| 49 | #endif /* DRIVERS_SPI_NAND_H */ |