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Bryan O'Donoghue75895292018-05-25 17:36:56 +01001/*
2 * Copyright (c) Linaro 2018 Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00006#ifndef IMX_UART_H
7#define IMX_UART_H
Bryan O'Donoghue75895292018-05-25 17:36:56 +01008
Ying-Chun Liu (PaulLiu)26ca4f52019-02-12 18:33:04 +08009#include <drivers/console.h>
10
Bryan O'Donoghue75895292018-05-25 17:36:56 +010011#define IMX_UART_RXD_OFFSET 0x00
12#define IMX_UART_RXD_CHARRDY BIT(15)
13#define IMX_UART_RXD_ERR BIT(14)
14#define IMX_UART_RXD_OVERRUN BIT(13)
15#define IMX_UART_RXD_FRMERR BIT(12)
16#define IMX_UART_RXD_BRK BIT(11)
17#define IMX_UART_RXD_PRERR BIT(10)
18
19#define IMX_UART_TXD_OFFSET 0x40
20
21#define IMX_UART_CR1_OFFSET 0x80
22#define IMX_UART_CR1_ADEN BIT(15)
23#define IMX_UART_CR1_ADBR BIT(14)
24#define IMX_UART_CR1_TRDYEN BIT(13)
25#define IMX_UART_CR1_IDEN BIT(12)
26#define IMX_UART_CR1_RRDYEN BIT(9)
27#define IMX_UART_CR1_RXDMAEN BIT(8)
28#define IMX_UART_CR1_IREN BIT(7)
29#define IMX_UART_CR1_TXMPTYEN BIT(6)
30#define IMX_UART_CR1_RTSDEN BIT(5)
31#define IMX_UART_CR1_SNDBRK BIT(4)
32#define IMX_UART_CR1_TXDMAEN BIT(3)
33#define IMX_UART_CR1_ATDMAEN BIT(2)
34#define IMX_UART_CR1_DOZE BIT(1)
35#define IMX_UART_CR1_UARTEN BIT(0)
36
37#define IMX_UART_CR2_OFFSET 0x84
38#define IMX_UART_CR2_ESCI BIT(15)
39#define IMX_UART_CR2_IRTS BIT(14)
40#define IMX_UART_CR2_CTSC BIT(13)
41#define IMX_UART_CR2_CTS BIT(12)
42#define IMX_UART_CR2_ESCEN BIT(11)
43#define IMX_UART_CR2_PREN BIT(8)
44#define IMX_UART_CR2_PROE BIT(7)
45#define IMX_UART_CR2_STPB BIT(6)
46#define IMX_UART_CR2_WS BIT(5)
47#define IMX_UART_CR2_RTSEN BIT(4)
48#define IMX_UART_CR2_ATEN BIT(3)
49#define IMX_UART_CR2_TXEN BIT(2)
50#define IMX_UART_CR2_RXEN BIT(1)
51#define IMX_UART_CR2_SRST BIT(0)
52
53#define IMX_UART_CR3_OFFSET 0x88
54#define IMX_UART_CR3_DTREN BIT(13)
55#define IMX_UART_CR3_PARERREN BIT(12)
56#define IMX_UART_CR3_FARERREN BIT(11)
57#define IMX_UART_CR3_DSD BIT(10)
58#define IMX_UART_CR3_DCD BIT(9)
59#define IMX_UART_CR3_RI BIT(8)
60#define IMX_UART_CR3_ADNIMP BIT(7)
61#define IMX_UART_CR3_RXDSEN BIT(6)
62#define IMX_UART_CR3_AIRINTEN BIT(5)
63#define IMX_UART_CR3_AWAKEN BIT(4)
64#define IMX_UART_CR3_DTRDEN BIT(3)
65#define IMX_UART_CR3_RXDMUXSEL BIT(2)
66#define IMX_UART_CR3_INVT BIT(1)
67#define IMX_UART_CR3_ACIEN BIT(0)
68
69#define IMX_UART_CR4_OFFSET 0x8c
70#define IMX_UART_CR4_INVR BIT(9)
71#define IMX_UART_CR4_ENIRI BIT(8)
72#define IMX_UART_CR4_WKEN BIT(7)
73#define IMX_UART_CR4_IDDMAEN BIT(6)
74#define IMX_UART_CR4_IRSC BIT(5)
75#define IMX_UART_CR4_LPBYP BIT(4)
76#define IMX_UART_CR4_TCEN BIT(3)
77#define IMX_UART_CR4_BKEN BIT(2)
78#define IMX_UART_CR4_OREN BIT(1)
79#define IMX_UART_CR4_DREN BIT(0)
80
81#define IMX_UART_FCR_OFFSET 0x90
82#define IMX_UART_FCR_TXTL_MASK (BIT(15) | BIT(14) | BIT(13) | BIT(12) |\
83 BIT(11) | BIT(10))
84#define IMX_UART_FCR_TXTL(x) ((x) << 10)
85#define IMX_UART_FCR_RFDIV_MASK (BIT(9) | BIT(8) | BIT(7))
86#define IMX_UART_FCR_RFDIV7 (BIT(9) | BIT(8))
87#define IMX_UART_FCR_RFDIV1 (BIT(9) | BIT(7))
88#define IMX_UART_FCR_RFDIV2 BIT(9)
89#define IMX_UART_FCR_RFDIV3 (BIT(8) | BIT(7))
90#define IMX_UART_FCR_RFDIV4 BIT(8)
91#define IMX_UART_FCR_RFDIV5 BIT(7)
92#define IMX_UART_FCR_RFDIV6 0
93#define IMX_UART_FCR_DCEDTE BIT(6)
94#define IMX_UART_FCR_RXTL_MASK (BIT(5) | BIT(4) | BIT(3) | BIT(2) |\
95 BIT(1) | BIT(0))
96#define IMX_UART_FCR_RXTL(x) x
97
98#define IMX_UART_STAT1_OFFSET 0x94
99#define IMX_UART_STAT1_PARITYERR BIT(15)
100#define IMX_UART_STAT1_RTSS BIT(14)
101#define IMX_UART_STAT1_TRDY BIT(13)
102#define IMX_UART_STAT1_RTSD BIT(12)
103#define IMX_UART_STAT1_ESCF BIT(11)
104#define IMX_UART_STAT1_FRAMEERR BIT(10)
105#define IMX_UART_STAT1_RRDY BIT(9)
106#define IMX_UART_STAT1_AGTIM BIT(8)
107#define IMX_UART_STAT1_DTRD BIT(7)
108#define IMX_UART_STAT1_RXDS BIT(6)
109#define IMX_UART_STAT1_AIRINT BIT(5)
110#define IMX_UART_STAT1_AWAKE BIT(4)
111#define IMX_UART_STAT1_SAD BIT(3)
112
113#define IMX_UART_STAT2_OFFSET 0x98
114#define IMX_UART_STAT2_ADET BIT(15)
115#define IMX_UART_STAT2_TXFE BIT(14)
116#define IMX_UART_STAT2_DTRF BIT(13)
117#define IMX_UART_STAT2_IDLE BIT(12)
118#define IMX_UART_STAT2_ACST BIT(11)
119#define IMX_UART_STAT2_RIDELT BIT(10)
120#define IMX_UART_STAT2_RIIN BIT(9)
121#define IMX_UART_STAT2_IRINT BIT(8)
122#define IMX_UART_STAT2_WAKE BIT(7)
123#define IMX_UART_STAT2_DCDDELT BIT(6)
124#define IMX_UART_STAT2_DCDIN BIT(5)
125#define IMX_UART_STAT2_RTSF BIT(4)
126#define IMX_UART_STAT2_TXDC BIT(3)
127#define IMX_UART_STAT2_BRCD BIT(2)
128#define IMX_UART_STAT2_ORE BIT(1)
129#define IMX_UART_STAT2_RCR BIT(0)
130
131#define IMX_UART_ESC_OFFSET 0x9c
132
133#define IMX_UART_TIM_OFFSET 0xa0
134
135#define IMX_UART_BIR_OFFSET 0xa4
136
137#define IMX_UART_BMR_OFFSET 0xa8
138
139#define IMX_UART_BRC_OFFSET 0xac
140
141#define IMX_UART_ONEMS_OFFSET 0xb0
142
143#define IMX_UART_TS_OFFSET 0xb4
144#define IMX_UART_TS_FRCPERR BIT(13)
145#define IMX_UART_TS_LOOP BIT(12)
146#define IMX_UART_TS_DBGEN BIT(11)
147#define IMX_UART_TS_LOOPIR BIT(10)
148#define IMX_UART_TS_RXDBG BIT(9)
149#define IMX_UART_TS_TXEMPTY BIT(6)
150#define IMX_UART_TS_RXEMPTY BIT(5)
151#define IMX_UART_TS_TXFULL BIT(4)
152#define IMX_UART_TS_RXFULL BIT(3)
153#define IMX_UART_TS_SOFTRST BIT(0)
154
Julius Werner53456fc2019-07-09 13:49:11 -0700155#ifndef __ASSEMBLER__
Ying-Chun Liu (PaulLiu)26ca4f52019-02-12 18:33:04 +0800156
Ying-Chun Liu (PaulLiu)26ca4f52019-02-12 18:33:04 +0800157int console_imx_uart_register(uintptr_t baseaddr,
158 uint32_t clock,
159 uint32_t baud,
Andre Przywara7110d992020-01-25 00:58:35 +0000160 console_t *console);
Julius Werner53456fc2019-07-09 13:49:11 -0700161#endif /*__ASSEMBLER__*/
Ying-Chun Liu (PaulLiu)26ca4f52019-02-12 18:33:04 +0800162
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000163#endif /* IMX_UART_H */