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git01.mediatek.com / filogic / atf / cc3e8b8fb6df0ac2e9a9bed76bc00217753df420 / . / plat / nvidia / tegra / soc / t194 / drivers / include / t194_nvg.h
blob: 1fe462032d70b89fd5377e55fc01b707c0435d47 [file] [log] [blame]
Steven Kao2cdb6782017-01-05 17:04:40 +0800[diff] [blame]1/*
2 * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef T194_NVG_H
8#define T194_NVG_H
9
10/**
11 * t194_nvg.h - Header for the NVIDIA Generic interface (NVG).
12 * Official documentation for this interface is included as part
13 * of the T194 TRM.
14 */
15
16/**
17 * Current version - Major version increments may break backwards
18 * compatiblity and binary compatibility. Minor version increments
19 * occur when there is only new functionality.
20 */
21enum {
22 TEGRA_NVG_VERSION_MAJOR = 6,
23 TEGRA_NVG_VERSION_MINOR = 0,
24};
25
26typedef enum {
27 TEGRA_NVG_CHANNEL_VERSION = 0,
28 TEGRA_NVG_CHANNEL_POWER_PERF = 1,
29 TEGRA_NVG_CHANNEL_POWER_MODES = 2,
30 TEGRA_NVG_CHANNEL_WAKE_TIME = 3,
31 TEGRA_NVG_CHANNEL_CSTATE_INFO = 4,
32 TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND = 5,
33 TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND = 6,
34 // Value 7 reserved
35 TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND = 8,
36 // Value 9 reserved
37 TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST = 10,
38 TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE = 11,
39 // Values 12-42 reserved
40 TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED = 43,
41 TEGRA_NVG_CHANNEL_ONLINE_CORE = 44,
42 TEGRA_NVG_CHANNEL_CC3_CTRL = 45,
43 TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC = 50,
44 TEGRA_NVG_CHANNEL_CCPLEX_CACHE_INVAL = 51,
45 // 52 FREQ FEEDBACK
46 TEGRA_NVG_CHANNEL_HSM_ERROR_CTRL = 53,
47 TEGRA_NVG_CHANNEL_SECURITY_CONFIG = 54,
48 TEGRA_NVG_CHANNEL_LAST_INDEX,
49} tegra_nvg_channel_id_t;
50
51
52typedef enum {
53 // Value 0 reserved
54 NVG_STAT_QUERY_SC7_ENTRIES = 1,
55 // Values 2-5 reserved
56 NVG_STAT_QUERY_CC6_ENTRIES = 6,
57 NVG_STAT_QUERY_CG7_ENTRIES = 7,
58 // Values 8-9 reserved
59 NVG_STAT_QUERY_C6_ENTRIES = 10,
60 // Values 11-13 reserved
61 NVG_STAT_QUERY_C7_ENTRIES = 14,
62 // Values 15-31 reserved
63 NVG_STAT_QUERY_SC7_RESIDENCY_SUM = 32,
64 NVG_STAT_QUERY_CC6_RESIDENCY_SUM = 41,
65 NVG_STAT_QUERY_CG7_RESIDENCY_SUM = 46,
66 NVG_STAT_QUERY_C6_RESIDENCY_SUM = 51,
67 NVG_STAT_QUERY_C7_RESIDENCY_SUM = 56,
68} tegra_nvg_stat_query_t;
69
70
71typedef enum {
72 TEGRA_NVG_CORE_C0 = 0,
73 TEGRA_NVG_CORE_C1 = 1,
74 TEGRA_NVG_CORE_C6 = 6,
75 TEGRA_NVG_CORE_C7 = 7,
76 TEGRA_NVG_CORE_WARMRSTREQ = 8,
77} tegra_nvg_core_sleep_state_t;
78
79typedef enum {
80 TEGRA_NVG_CLUSTER_CC0 = 0,
81 TEGRA_NVG_CLUSTER_CC6 = 6,
82} tegra_nvg_cluster_sleep_state_t;
83
84typedef enum {
85 TEGRA_NVG_CCPLEX_CG0 = 0,
86 TEGRA_NVG_CCPLEX_CG7 = 1,
87
88} tegra_nvg_cluster_group_sleep_state_t;
89
90typedef enum {
91 TEGRA_NVG_SYSTEM_SC0 = 0,
92 TEGRA_NVG_SYSTEM_SC7 = 7,
93 TEGRA_NVG_SYSTEM_SC8 = 8,
94} tegra_nvg_system_sleep_state_t;
95
96// ---------------------------------------------------------------------------
97// NVG Data subformats
98// ---------------------------------------------------------------------------
99
100typedef union
101{
102 uint64_t flat;
103 struct nvg_version_channel_t {
104 uint64_t minor_version : 32;
105 uint64_t major_version : 32;
106 } bits;
107} nvg_version_data_t;
108
109typedef union nvg_channel_1_data_u
110{
111 uint64_t flat;
112 struct nvg_channel_1_data_s
113 {
114 uint64_t perf_per_watt_mode : 1;
115 uint64_t reserved_63_1 : 63;
116 } bits;
117} nvg_channel_1_data_t;
118
119typedef union nvg_channel_2_data_u
120{
121 uint64_t flat;
122 struct nvg_channel_2_data_s
123 {
124 uint64_t reserved_1_0 : 2;
125 uint64_t battery_saver_mode : 1;
126 uint64_t reserved_63_3 : 61;
127 } bits;
128} nvg_channel_2_data_t;
129
130typedef union
131{
132 uint64_t flat;
133 struct nvg_wake_time_channel_t {
134 uint64_t wake_time : 32;
135 uint64_t reserved_63_32 : 32;
136 } bits;
137} nvg_wake_time_channel_t;
138
139typedef union
140{
141 uint64_t flat;
142 struct nvg_cstate_info_channel_t {
143 uint64_t cluster_state : 3;
144 uint64_t reserved_6_3 : 4;
145 uint64_t update_cluster : 1;
146 uint64_t cg_cstate : 3;
147 uint64_t reserved_14_11 : 4;
148 uint64_t update_cg : 1;
149 uint64_t system_cstate : 4;
150 uint64_t reserved_22_20 : 3;
151 uint64_t update_system : 1;
152 uint64_t reserved_30_24 : 7;
153 uint64_t update_wake_mask : 1;
154 uint64_t wake_mask : 32;
155 } bits;
156} nvg_cstate_info_channel_t;
157
158typedef union
159{
160 uint64_t flat;
161 struct nvg_lower_bound_channel_t {
162 uint64_t crossover_value : 32;
163 uint64_t reserved_63_32 : 32;
164 } bits;
165} nvg_lower_bound_channel_t;
166
167
168typedef union
169{
170 uint64_t flat;
171 struct nvg_cstate_stat_query_channel_t {
172 uint64_t unit_id : 4;
173 uint64_t reserved_15_4 : 12;
174 uint64_t stat_id : 16;
175 uint64_t reserved_63_32 : 32;
176 } bits;
177} nvg_cstate_stat_query_channel_t;
178
179typedef union
180{
181 uint64_t flat;
182 struct nvg_is_sc7_allowed_channel_t {
183 uint64_t is_sc7_allowed : 1;
184 uint64_t reserved_63_32 : 63;
185 } bits;
186} nvg_is_sc7_allowed_channel_t;
187
188
189typedef union
190{
191 uint64_t flat;
192 struct nvg_core_online_channel_t {
193 uint64_t core_id : 4;
194 uint64_t reserved_63_4 : 60;
195 } bits;
196} nvg_core_online_channel_t;
197
198
199typedef union
200{
201 uint64_t flat;
202 struct nvg_cc3_control_channel_t {
203 uint64_t freq_req : 8;
204 uint64_t reserved_30_8 : 23;
205 uint64_t enable : 1;
206 uint64_t reserved_63_32 : 32;
207 } bits;
208} nvg_cc3_control_channel_t;
209
210
211typedef union
212{
213 uint64_t flat;
214 struct nvg_update_gsc_channel_t {
215 uint64_t gsc_enum : 16;
216 uint64_t reserved_63_16 : 48;
217 } bits;
218} nvg_update_gsc_channel_t;
219
220
221typedef union
222{
223 uint64_t flat;
224 struct nvg_cache_inval_channel_t {
225 uint64_t cache_clean : 1;
226 uint64_t cache_clean_inval : 1;
227 uint64_t cache_clean_inval_tr : 1;
228 uint64_t reserved_63_3 : 61;
229 } bits;
230} nvg_cache_inval_channel_t;
231
232
233/* GSC type define */
234typedef enum {
235 TEGRA_NVG_GSC_ALL=0,
236 TEGRA_NVG_GSC_NVDEC=1,
237 TEGRA_NVG_GSC_WPR1=2,
238 TEGRA_NVG_GSC_WPR2=3,
239 TEGRA_NVG_GSC_TSECA=4,
240 TEGRA_NVG_GSC_TSECB=5,
241
242 TEGRA_NVG_GSC_BPMP=6,
243 TEGRA_NVG_GSC_APE=7,
244 TEGRA_NVG_GSC_SPE=8,
245 TEGRA_NVG_GSC_SCE=9,
246 TEGRA_NVG_GSC_APR=10,
247 TEGRA_NVG_GSC_TZRAM=11,
248 TEGRA_NVG_GSC_SE=12,
249
250 TEGRA_NVG_GSC_DMCE=13,
251 TEGRA_NVG_GSC_BPMP_TO_DMCE=14,
252 TEGRA_NVG_GSC_BPMP_TO_SPE=16,
253 TEGRA_NVG_GSC_CPU_TZ_TO_BPMP=18,
254 TEGRA_NVG_GSC_CPU_NS_TO_BPMP=20,
255 TEGRA_NVG_GSC_IPC_SE_SPE_SCE_BPMP=22,
256 TEGRA_NVG_GSC_SC7_RESUME_FW=23,
257
258 TEGRA_NVG_GSC_VPR_RESIZE=24,
259 TEGRA_NVG_GSC_RCE=25,
260 TEGRA_NVG_GSC_CV=26,
261
262 TEGRA_NVG_GSC_BO_MTS_PACKAGE=28,
263 TEGRA_NVG_GSC_BO_MCE_PREBOOT=29,
264
265 TEGRA_NVG_GSC_TZ_DRAM_IDX=34,
266 TEGRA_NVG_GSC_VPR_IDX=35,
267} tegra_nvg_gsc_index_t;
268
269typedef enum {
270 TEGRA_NVG_CROSSOVER_C6 = 0,
271 TEGRA_NVG_CROSSOVER_CC6 = 1,
272 TEGRA_NVG_CROSSOVER_CG7 = 2,
273} tegra_nvg_crossover_index_t;
274
275#endif // T194_NVG_H