blob: 98b91c39f6c8b7cd1e168433659efbeb7482ed48 [file] [log] [blame]
Andre Przywara13815472018-06-01 02:01:39 +01001/*
Samuel Hollandf93a9ab2020-12-13 21:56:15 -06002 * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
Andre Przywara13815472018-06-01 02:01:39 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <common/debug.h>
8#include <lib/mmio.h>
9
Samuel Hollandf1be8402020-12-13 21:44:54 -060010#include <sunxi_ccu.h>
Andre Przywara13815472018-06-01 02:01:39 +010011#include <sunxi_mmap.h>
Andre Przywara456208a2018-10-14 12:02:02 +010012#include <sunxi_private.h>
Samuel Hollandf93a9ab2020-12-13 21:56:15 -060013#include <sunxi_spc.h>
Andre Przywara13815472018-06-01 02:01:39 +010014
Andre Przywara13815472018-06-01 02:01:39 +010015#define DMA_SEC_REG 0x20
16
17/*
18 * Setup the peripherals to be accessible by non-secure world.
19 * This will not work for the Secure Peripherals Controller (SPC) unless
20 * a fuse it burnt (seems to be an erratum), but we do it nevertheless,
21 * to allow booting on boards using secure boot.
22 */
23void sunxi_security_setup(void)
24{
25 int i;
26
Andre Przywara13815472018-06-01 02:01:39 +010027 INFO("Configuring SPC Controller\n");
28 /* SPC setup: set all devices to non-secure */
Samuel Hollandf93a9ab2020-12-13 21:56:15 -060029 for (i = 0; i < SUNXI_SPC_NUM_PORTS; i++)
30 mmio_write_32(SUNXI_SPC_DECPORT_SET_REG(i), 0xffffffff);
Andre Przywara13815472018-06-01 02:01:39 +010031
32 /* set MBUS clocks, bus clocks (AXI/AHB/APB) and PLLs to non-secure */
33 mmio_write_32(SUNXI_CCU_SEC_SWITCH_REG, 0x7);
34
Samuel Holland62d401a2019-12-29 16:12:12 -060035 /* Set R_PRCM bus clocks to non-secure */
Samuel Hollandf1be8402020-12-13 21:44:54 -060036 mmio_write_32(SUNXI_R_PRCM_SEC_SWITCH_REG, 0x1);
Andre Przywara13815472018-06-01 02:01:39 +010037
38 /* Set all DMA channels (16 max.) to non-secure */
39 mmio_write_32(SUNXI_DMA_BASE + DMA_SEC_REG, 0xffff);
40}