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Dan Handley610e7e12018-03-01 18:44:00 +00001Trusted Firmware-A design
2=========================
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003
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5.. section-numbering::
6 :suffix: .
7
8.. contents::
9
Dan Handley610e7e12018-03-01 18:44:00 +000010Trusted Firmware-A (TF-A) implements a subset of the Trusted Board Boot
11Requirements (TBBR) Platform Design Document (PDD) [1]_ for Arm reference
Douglas Raillardd7c21b72017-06-28 15:23:03 +010012platforms. The TBB sequence starts when the platform is powered on and runs up
13to the stage where it hands-off control to firmware running in the normal
14world in DRAM. This is the cold boot path.
15
Dan Handley610e7e12018-03-01 18:44:00 +000016TF-A also implements the Power State Coordination Interface PDD [2]_ as a
17runtime service. PSCI is the interface from normal world software to firmware
18implementing power management use-cases (for example, secondary CPU boot,
19hotplug and idle). Normal world software can access TF-A runtime services via
20the Arm SMC (Secure Monitor Call) instruction. The SMC instruction must be
21used as mandated by the SMC Calling Convention [3]_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010022
Dan Handley610e7e12018-03-01 18:44:00 +000023TF-A implements a framework for configuring and managing interrupts generated
24in either security state. The details of the interrupt management framework
25and its design can be found in TF-A Interrupt Management Design guide [4]_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010026
Dan Handley610e7e12018-03-01 18:44:00 +000027TF-A also implements a library for setting up and managing the translation
28tables. The details of this library can be found in `Xlat_tables design`_.
Antonio Nino Diazb5d68092017-05-23 11:49:22 +010029
Dan Handley610e7e12018-03-01 18:44:00 +000030TF-A can be built to support either AArch64 or AArch32 execution state.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010031
32Cold boot
33---------
34
35The cold boot path starts when the platform is physically turned on. If
36``COLD_BOOT_SINGLE_CPU=0``, one of the CPUs released from reset is chosen as the
37primary CPU, and the remaining CPUs are considered secondary CPUs. The primary
38CPU is chosen through platform-specific means. The cold boot path is mainly
39executed by the primary CPU, other than essential CPU initialization executed by
40all CPUs. The secondary CPUs are kept in a safe platform-specific state until
41the primary CPU has performed enough initialization to boot them.
42
43Refer to the `Reset Design`_ for more information on the effect of the
44``COLD_BOOT_SINGLE_CPU`` platform build option.
45
Dan Handley610e7e12018-03-01 18:44:00 +000046The cold boot path in this implementation of TF-A depends on the execution
47state. For AArch64, it is divided into five steps (in order of execution):
Douglas Raillardd7c21b72017-06-28 15:23:03 +010048
49- Boot Loader stage 1 (BL1) *AP Trusted ROM*
50- Boot Loader stage 2 (BL2) *Trusted Boot Firmware*
51- Boot Loader stage 3-1 (BL31) *EL3 Runtime Software*
52- Boot Loader stage 3-2 (BL32) *Secure-EL1 Payload* (optional)
53- Boot Loader stage 3-3 (BL33) *Non-trusted Firmware*
54
55For AArch32, it is divided into four steps (in order of execution):
56
57- Boot Loader stage 1 (BL1) *AP Trusted ROM*
58- Boot Loader stage 2 (BL2) *Trusted Boot Firmware*
59- Boot Loader stage 3-2 (BL32) *EL3 Runtime Software*
60- Boot Loader stage 3-3 (BL33) *Non-trusted Firmware*
61
Dan Handley610e7e12018-03-01 18:44:00 +000062Arm development platforms (Fixed Virtual Platforms (FVPs) and Juno) implement a
Douglas Raillardd7c21b72017-06-28 15:23:03 +010063combination of the following types of memory regions. Each bootloader stage uses
64one or more of these memory regions.
65
66- Regions accessible from both non-secure and secure states. For example,
67 non-trusted SRAM, ROM and DRAM.
68- Regions accessible from only the secure state. For example, trusted SRAM and
69 ROM. The FVPs also implement the trusted DRAM which is statically
70 configured. Additionally, the Base FVPs and Juno development platform
71 configure the TrustZone Controller (TZC) to create a region in the DRAM
72 which is accessible only from the secure state.
73
74The sections below provide the following details:
75
Soby Mathewb1bf0442018-02-16 14:52:52 +000076- dynamic configuration of Boot Loader stages
Douglas Raillardd7c21b72017-06-28 15:23:03 +010077- initialization and execution of the first three stages during cold boot
78- specification of the EL3 Runtime Software (BL31 for AArch64 and BL32 for
79 AArch32) entrypoint requirements for use by alternative Trusted Boot
80 Firmware in place of the provided BL1 and BL2
81
Soby Mathewb1bf0442018-02-16 14:52:52 +000082Dynamic Configuration during cold boot
83~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
84
85Each of the Boot Loader stages may be dynamically configured if required by the
86platform. The Boot Loader stage may optionally specify a firmware
87configuration file and/or hardware configuration file as listed below:
88
89- HW_CONFIG - The hardware configuration file. Can be shared by all Boot Loader
90 stages and also by the Normal World Rich OS.
91- TB_FW_CONFIG - Trusted Boot Firmware configuration file. Shared between BL1
92 and BL2.
93- SOC_FW_CONFIG - SoC Firmware configuration file. Used by BL31.
94- TOS_FW_CONFIG - Trusted OS Firmware configuration file. Used by Trusted OS
95 (BL32).
96- NT_FW_CONFIG - Non Trusted Firmware configuration file. Used by Non-trusted
97 firmware (BL33).
98
99The Arm development platforms use the Flattened Device Tree format for the
100dynamic configuration files.
101
102Each Boot Loader stage can pass up to 4 arguments via registers to the next
103stage. BL2 passes the list of the next images to execute to the *EL3 Runtime
104Software* (BL31 for AArch64 and BL32 for AArch32) via `arg0`. All the other
105arguments are platform defined. The Arm development platforms use the following
106convention:
107
108- BL1 passes the address of a meminfo_t structure to BL2 via ``arg1``. This
109 structure contains the memory layout available to BL2.
110- When dynamic configuration files are present, the firmware configuration for
111 the next Boot Loader stage is populated in the first available argument and
112 the generic hardware configuration is passed the next available argument.
113 For example,
114
115 - If TB_FW_CONFIG is loaded by BL1, then its address is passed in ``arg0``
116 to BL2.
117 - If HW_CONFIG is loaded by BL1, then its address is passed in ``arg2`` to
118 BL2. Note, ``arg1`` is already used for meminfo_t.
119 - If SOC_FW_CONFIG is loaded by BL2, then its address is passed in ``arg1``
120 to BL31. Note, ``arg0`` is used to pass the list of executable images.
121 - Similarly, if HW_CONFIG is loaded by BL1 or BL2, then its address is
122 passed in ``arg2`` to BL31.
123 - For other BL3x images, if the firmware configuration file is loaded by
124 BL2, then its address is passed in ``arg0`` and if HW_CONFIG is loaded
125 then its address is passed in ``arg1``.
126
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100127BL1
128~~~
129
130This stage begins execution from the platform's reset vector at EL3. The reset
131address is platform dependent but it is usually located in a Trusted ROM area.
132The BL1 data section is copied to trusted SRAM at runtime.
133
Dan Handley610e7e12018-03-01 18:44:00 +0000134On the Arm development platforms, BL1 code starts execution from the reset
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100135vector defined by the constant ``BL1_RO_BASE``. The BL1 data section is copied
136to the top of trusted SRAM as defined by the constant ``BL1_RW_BASE``.
137
138The functionality implemented by this stage is as follows.
139
140Determination of boot path
141^^^^^^^^^^^^^^^^^^^^^^^^^^
142
143Whenever a CPU is released from reset, BL1 needs to distinguish between a warm
144boot and a cold boot. This is done using platform-specific mechanisms (see the
145``plat_get_my_entrypoint()`` function in the `Porting Guide`_). In the case of a
146warm boot, a CPU is expected to continue execution from a separate
147entrypoint. In the case of a cold boot, the secondary CPUs are placed in a safe
148platform-specific state (see the ``plat_secondary_cold_boot_setup()`` function in
149the `Porting Guide`_) while the primary CPU executes the remaining cold boot path
150as described in the following sections.
151
152This step only applies when ``PROGRAMMABLE_RESET_ADDRESS=0``. Refer to the
153`Reset Design`_ for more information on the effect of the
154``PROGRAMMABLE_RESET_ADDRESS`` platform build option.
155
156Architectural initialization
157^^^^^^^^^^^^^^^^^^^^^^^^^^^^
158
159BL1 performs minimal architectural initialization as follows.
160
161- Exception vectors
162
163 BL1 sets up simple exception vectors for both synchronous and asynchronous
164 exceptions. The default behavior upon receiving an exception is to populate
165 a status code in the general purpose register ``X0/R0`` and call the
166 ``plat_report_exception()`` function (see the `Porting Guide`_). The status
167 code is one of:
168
169 For AArch64:
170
171 ::
172
173 0x0 : Synchronous exception from Current EL with SP_EL0
174 0x1 : IRQ exception from Current EL with SP_EL0
175 0x2 : FIQ exception from Current EL with SP_EL0
176 0x3 : System Error exception from Current EL with SP_EL0
177 0x4 : Synchronous exception from Current EL with SP_ELx
178 0x5 : IRQ exception from Current EL with SP_ELx
179 0x6 : FIQ exception from Current EL with SP_ELx
180 0x7 : System Error exception from Current EL with SP_ELx
181 0x8 : Synchronous exception from Lower EL using aarch64
182 0x9 : IRQ exception from Lower EL using aarch64
183 0xa : FIQ exception from Lower EL using aarch64
184 0xb : System Error exception from Lower EL using aarch64
185 0xc : Synchronous exception from Lower EL using aarch32
186 0xd : IRQ exception from Lower EL using aarch32
187 0xe : FIQ exception from Lower EL using aarch32
188 0xf : System Error exception from Lower EL using aarch32
189
190 For AArch32:
191
192 ::
193
194 0x10 : User mode
195 0x11 : FIQ mode
196 0x12 : IRQ mode
197 0x13 : SVC mode
198 0x16 : Monitor mode
199 0x17 : Abort mode
200 0x1a : Hypervisor mode
201 0x1b : Undefined mode
202 0x1f : System mode
203
Dan Handley610e7e12018-03-01 18:44:00 +0000204 The ``plat_report_exception()`` implementation on the Arm FVP port programs
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100205 the Versatile Express System LED register in the following format to
206 indicate the occurence of an unexpected exception:
207
208 ::
209
210 SYS_LED[0] - Security state (Secure=0/Non-Secure=1)
211 SYS_LED[2:1] - Exception Level (EL3=0x3, EL2=0x2, EL1=0x1, EL0=0x0)
212 For AArch32 it is always 0x0
213 SYS_LED[7:3] - Exception Class (Sync/Async & origin). This is the value
214 of the status code
215
216 A write to the LED register reflects in the System LEDs (S6LED0..7) in the
217 CLCD window of the FVP.
218
219 BL1 does not expect to receive any exceptions other than the SMC exception.
220 For the latter, BL1 installs a simple stub. The stub expects to receive a
221 limited set of SMC types (determined by their function IDs in the general
222 purpose register ``X0/R0``):
223
224 - ``BL1_SMC_RUN_IMAGE``: This SMC is raised by BL2 to make BL1 pass control
225 to EL3 Runtime Software.
226 - All SMCs listed in section "BL1 SMC Interface" in the `Firmware Update`_
227 Design Guide are supported for AArch64 only. These SMCs are currently
228 not supported when BL1 is built for AArch32.
229
230 Any other SMC leads to an assertion failure.
231
232- CPU initialization
233
234 BL1 calls the ``reset_handler()`` function which in turn calls the CPU
235 specific reset handler function (see the section: "CPU specific operations
236 framework").
237
238- Control register setup (for AArch64)
239
240 - ``SCTLR_EL3``. Instruction cache is enabled by setting the ``SCTLR_EL3.I``
241 bit. Alignment and stack alignment checking is enabled by setting the
242 ``SCTLR_EL3.A`` and ``SCTLR_EL3.SA`` bits. Exception endianness is set to
243 little-endian by clearing the ``SCTLR_EL3.EE`` bit.
244
245 - ``SCR_EL3``. The register width of the next lower exception level is set
246 to AArch64 by setting the ``SCR.RW`` bit. The ``SCR.EA`` bit is set to trap
247 both External Aborts and SError Interrupts in EL3. The ``SCR.SIF`` bit is
248 also set to disable instruction fetches from Non-secure memory when in
249 secure state.
250
251 - ``CPTR_EL3``. Accesses to the ``CPACR_EL1`` register from EL1 or EL2, or the
252 ``CPTR_EL2`` register from EL2 are configured to not trap to EL3 by
253 clearing the ``CPTR_EL3.TCPAC`` bit. Access to the trace functionality is
254 configured not to trap to EL3 by clearing the ``CPTR_EL3.TTA`` bit.
255 Instructions that access the registers associated with Floating Point
256 and Advanced SIMD execution are configured to not trap to EL3 by
257 clearing the ``CPTR_EL3.TFP`` bit.
258
259 - ``DAIF``. The SError interrupt is enabled by clearing the SError interrupt
260 mask bit.
261
262 - ``MDCR_EL3``. The trap controls, ``MDCR_EL3.TDOSA``, ``MDCR_EL3.TDA`` and
263 ``MDCR_EL3.TPM``, are set so that accesses to the registers they control
264 do not trap to EL3. AArch64 Secure self-hosted debug is disabled by
265 setting the ``MDCR_EL3.SDD`` bit. Also ``MDCR_EL3.SPD32`` is set to
266 disable AArch32 Secure self-hosted privileged debug from S-EL1.
267
268- Control register setup (for AArch32)
269
270 - ``SCTLR``. Instruction cache is enabled by setting the ``SCTLR.I`` bit.
271 Alignment checking is enabled by setting the ``SCTLR.A`` bit.
272 Exception endianness is set to little-endian by clearing the
273 ``SCTLR.EE`` bit.
274
275 - ``SCR``. The ``SCR.SIF`` bit is set to disable instruction fetches from
276 Non-secure memory when in secure state.
277
278 - ``CPACR``. Allow execution of Advanced SIMD instructions at PL0 and PL1,
279 by clearing the ``CPACR.ASEDIS`` bit. Access to the trace functionality
280 is configured not to trap to undefined mode by clearing the
281 ``CPACR.TRCDIS`` bit.
282
283 - ``NSACR``. Enable non-secure access to Advanced SIMD functionality and
284 system register access to implemented trace registers.
285
286 - ``FPEXC``. Enable access to the Advanced SIMD and floating-point
287 functionality from all Exception levels.
288
289 - ``CPSR.A``. The Asynchronous data abort interrupt is enabled by clearing
290 the Asynchronous data abort interrupt mask bit.
291
292 - ``SDCR``. The ``SDCR.SPD`` field is set to disable AArch32 Secure
293 self-hosted privileged debug.
294
295Platform initialization
296^^^^^^^^^^^^^^^^^^^^^^^
297
Dan Handley610e7e12018-03-01 18:44:00 +0000298On Arm platforms, BL1 performs the following platform initializations:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100299
300- Enable the Trusted Watchdog.
301- Initialize the console.
302- Configure the Interconnect to enable hardware coherency.
303- Enable the MMU and map the memory it needs to access.
304- Configure any required platform storage to load the next bootloader image
305 (BL2).
Soby Mathewb1bf0442018-02-16 14:52:52 +0000306- If the BL1 dynamic configuration file, ``TB_FW_CONFIG``, is available, then
307 load it to the platform defined address and make it available to BL2 via
308 ``arg0``.
Soby Mathewd969a7e2018-06-11 16:40:36 +0100309- Configure the system timer and program the `CNTFRQ_EL0` for use by NS-BL1U
310 and NS-BL2U firmware update images.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100311
312Firmware Update detection and execution
313^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
314
315After performing platform setup, BL1 common code calls
316``bl1_plat_get_next_image_id()`` to determine if `Firmware Update`_ is required or
317to proceed with the normal boot process. If the platform code returns
318``BL2_IMAGE_ID`` then the normal boot sequence is executed as described in the
319next section, else BL1 assumes that `Firmware Update`_ is required and execution
320passes to the first image in the `Firmware Update`_ process. In either case, BL1
321retrieves a descriptor of the next image by calling ``bl1_plat_get_image_desc()``.
322The image descriptor contains an ``entry_point_info_t`` structure, which BL1
323uses to initialize the execution state of the next image.
324
325BL2 image load and execution
326^^^^^^^^^^^^^^^^^^^^^^^^^^^^
327
328In the normal boot flow, BL1 execution continues as follows:
329
330#. BL1 prints the following string from the primary CPU to indicate successful
331 execution of the BL1 stage:
332
333 ::
334
335 "Booting Trusted Firmware"
336
Soby Mathewb1bf0442018-02-16 14:52:52 +0000337#. BL1 loads a BL2 raw binary image from platform storage, at a
338 platform-specific base address. Prior to the load, BL1 invokes
339 ``bl1_plat_handle_pre_image_load()`` which allows the platform to update or
340 use the image information. If the BL2 image file is not present or if
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100341 there is not enough free trusted SRAM the following error message is
342 printed:
343
344 ::
345
346 "Failed to load BL2 firmware."
347
Soby Mathewb1bf0442018-02-16 14:52:52 +0000348#. BL1 invokes ``bl1_plat_handle_post_image_load()`` which again is intended
349 for platforms to take further action after image load. This function must
350 populate the necessary arguments for BL2, which may also include the memory
351 layout. Further description of the memory layout can be found later
352 in this document.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100353
354#. BL1 passes control to the BL2 image at Secure EL1 (for AArch64) or at
355 Secure SVC mode (for AArch32), starting from its load address.
356
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100357BL2
358~~~
359
360BL1 loads and passes control to BL2 at Secure-EL1 (for AArch64) or at Secure
361SVC mode (for AArch32) . BL2 is linked against and loaded at a platform-specific
362base address (more information can be found later in this document).
363The functionality implemented by BL2 is as follows.
364
365Architectural initialization
366^^^^^^^^^^^^^^^^^^^^^^^^^^^^
367
368For AArch64, BL2 performs the minimal architectural initialization required
Dan Handley610e7e12018-03-01 18:44:00 +0000369for subsequent stages of TF-A and normal world software. EL1 and EL0 are given
370access to Floating Point and Advanced SIMD registers by clearing the
371``CPACR.FPEN`` bits.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100372
373For AArch32, the minimal architectural initialization required for subsequent
Dan Handley610e7e12018-03-01 18:44:00 +0000374stages of TF-A and normal world software is taken care of in BL1 as both BL1
375and BL2 execute at PL1.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100376
377Platform initialization
378^^^^^^^^^^^^^^^^^^^^^^^
379
Dan Handley610e7e12018-03-01 18:44:00 +0000380On Arm platforms, BL2 performs the following platform initializations:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100381
382- Initialize the console.
383- Configure any required platform storage to allow loading further bootloader
384 images.
385- Enable the MMU and map the memory it needs to access.
386- Perform platform security setup to allow access to controlled components.
387- Reserve some memory for passing information to the next bootloader image
388 EL3 Runtime Software and populate it.
389- Define the extents of memory available for loading each subsequent
390 bootloader image.
Soby Mathewb1bf0442018-02-16 14:52:52 +0000391- If BL1 has passed TB_FW_CONFIG dynamic configuration file in ``arg0``,
392 then parse it.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100393
394Image loading in BL2
395^^^^^^^^^^^^^^^^^^^^
396
Roberto Vargas025946a2018-09-24 17:20:48 +0100397BL2 generic code loads the images based on the list of loadable images
398provided by the platform. BL2 passes the list of executable images
399provided by the platform to the next handover BL image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100400
Soby Mathewb1bf0442018-02-16 14:52:52 +0000401The list of loadable images provided by the platform may also contain
402dynamic configuration files. The files are loaded and can be parsed as
403needed in the ``bl2_plat_handle_post_image_load()`` function. These
404configuration files can be passed to next Boot Loader stages as arguments
405by updating the corresponding entrypoint information in this function.
406
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100407SCP\_BL2 (System Control Processor Firmware) image load
408^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
409
410Some systems have a separate System Control Processor (SCP) for power, clock,
411reset and system control. BL2 loads the optional SCP\_BL2 image from platform
412storage into a platform-specific region of secure memory. The subsequent
Dan Handley610e7e12018-03-01 18:44:00 +0000413handling of SCP\_BL2 is platform specific. For example, on the Juno Arm
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100414development platform port the image is transferred into SCP's internal memory
415using the Boot Over MHU (BOM) protocol after being loaded in the trusted SRAM
416memory. The SCP executes SCP\_BL2 and signals to the Application Processor (AP)
417for BL2 execution to continue.
418
419EL3 Runtime Software image load
420^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
421
422BL2 loads the EL3 Runtime Software image from platform storage into a platform-
423specific address in trusted SRAM. If there is not enough memory to load the
Roberto Vargas025946a2018-09-24 17:20:48 +0100424image or image is missing it leads to an assertion failure.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100425
426AArch64 BL32 (Secure-EL1 Payload) image load
427^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
428
429BL2 loads the optional BL32 image from platform storage into a platform-
430specific region of secure memory. The image executes in the secure world. BL2
431relies on BL31 to pass control to the BL32 image, if present. Hence, BL2
432populates a platform-specific area of memory with the entrypoint/load-address
433of the BL32 image. The value of the Saved Processor Status Register (``SPSR``)
434for entry into BL32 is not determined by BL2, it is initialized by the
435Secure-EL1 Payload Dispatcher (see later) within BL31, which is responsible for
436managing interaction with BL32. This information is passed to BL31.
437
438BL33 (Non-trusted Firmware) image load
439^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
440
441BL2 loads the BL33 image (e.g. UEFI or other test or boot software) from
442platform storage into non-secure memory as defined by the platform.
443
444BL2 relies on EL3 Runtime Software to pass control to BL33 once secure state
445initialization is complete. Hence, BL2 populates a platform-specific area of
446memory with the entrypoint and Saved Program Status Register (``SPSR``) of the
447normal world software image. The entrypoint is the load address of the BL33
448image. The ``SPSR`` is determined as specified in Section 5.13 of the
449`PSCI PDD`_. This information is passed to the EL3 Runtime Software.
450
451AArch64 BL31 (EL3 Runtime Software) execution
452^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
453
454BL2 execution continues as follows:
455
456#. BL2 passes control back to BL1 by raising an SMC, providing BL1 with the
457 BL31 entrypoint. The exception is handled by the SMC exception handler
458 installed by BL1.
459
460#. BL1 turns off the MMU and flushes the caches. It clears the
461 ``SCTLR_EL3.M/I/C`` bits, flushes the data cache to the point of coherency
462 and invalidates the TLBs.
463
464#. BL1 passes control to BL31 at the specified entrypoint at EL3.
465
Roberto Vargasb1584272017-11-20 13:36:10 +0000466Running BL2 at EL3 execution level
467~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
468
Dan Handley610e7e12018-03-01 18:44:00 +0000469Some platforms have a non-TF-A Boot ROM that expects the next boot stage
470to execute at EL3. On these platforms, TF-A BL1 is a waste of memory
471as its only purpose is to ensure TF-A BL2 is entered at S-EL1. To avoid
Roberto Vargasb1584272017-11-20 13:36:10 +0000472this waste, a special mode enables BL2 to execute at EL3, which allows
Dan Handley610e7e12018-03-01 18:44:00 +0000473a non-TF-A Boot ROM to load and jump directly to BL2. This mode is selected
Roberto Vargasb1584272017-11-20 13:36:10 +0000474when the build flag BL2_AT_EL3 is enabled. The main differences in this
475mode are:
476
477#. BL2 includes the reset code and the mailbox mechanism to differentiate
478 cold boot and warm boot. It runs at EL3 doing the arch
479 initialization required for EL3.
480
481#. BL2 does not receive the meminfo information from BL1 anymore. This
482 information can be passed by the Boot ROM or be internal to the
483 BL2 image.
484
485#. Since BL2 executes at EL3, BL2 jumps directly to the next image,
486 instead of invoking the RUN_IMAGE SMC call.
487
488
489We assume 3 different types of BootROM support on the platform:
490
491#. The Boot ROM always jumps to the same address, for both cold
492 and warm boot. In this case, we will need to keep a resident part
493 of BL2 whose memory cannot be reclaimed by any other image. The
494 linker script defines the symbols __TEXT_RESIDENT_START__ and
495 __TEXT_RESIDENT_END__ that allows the platform to configure
496 correctly the memory map.
497#. The platform has some mechanism to indicate the jump address to the
498 Boot ROM. Platform code can then program the jump address with
499 psci_warmboot_entrypoint during cold boot.
500#. The platform has some mechanism to program the reset address using
501 the PROGRAMMABLE_RESET_ADDRESS feature. Platform code can then
502 program the reset address with psci_warmboot_entrypoint during
503 cold boot, bypassing the boot ROM for warm boot.
504
505In the last 2 cases, no part of BL2 needs to remain resident at
506runtime. In the first 2 cases, we expect the Boot ROM to be able to
507differentiate between warm and cold boot, to avoid loading BL2 again
508during warm boot.
509
510This functionality can be tested with FVP loading the image directly
511in memory and changing the address where the system jumps at reset.
512For example:
513
Dimitris Papastamos25836492018-06-11 11:07:58 +0100514 -C cluster0.cpu0.RVBAR=0x4022000
515 --data cluster0.cpu0=bl2.bin@0x4022000
Roberto Vargasb1584272017-11-20 13:36:10 +0000516
517With this configuration, FVP is like a platform of the first case,
518where the Boot ROM jumps always to the same address. For simplification,
519BL32 is loaded in DRAM in this case, to avoid other images reclaiming
520BL2 memory.
521
522
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100523AArch64 BL31
524~~~~~~~~~~~~
525
526The image for this stage is loaded by BL2 and BL1 passes control to BL31 at
527EL3. BL31 executes solely in trusted SRAM. BL31 is linked against and
528loaded at a platform-specific base address (more information can be found later
529in this document). The functionality implemented by BL31 is as follows.
530
531Architectural initialization
532^^^^^^^^^^^^^^^^^^^^^^^^^^^^
533
534Currently, BL31 performs a similar architectural initialization to BL1 as
535far as system register settings are concerned. Since BL1 code resides in ROM,
536architectural initialization in BL31 allows override of any previous
537initialization done by BL1.
538
539BL31 initializes the per-CPU data framework, which provides a cache of
540frequently accessed per-CPU data optimised for fast, concurrent manipulation
541on different CPUs. This buffer includes pointers to per-CPU contexts, crash
542buffer, CPU reset and power down operations, PSCI data, platform data and so on.
543
544It then replaces the exception vectors populated by BL1 with its own. BL31
545exception vectors implement more elaborate support for handling SMCs since this
546is the only mechanism to access the runtime services implemented by BL31 (PSCI
547for example). BL31 checks each SMC for validity as specified by the
548`SMC calling convention PDD`_ before passing control to the required SMC
549handler routine.
550
551BL31 programs the ``CNTFRQ_EL0`` register with the clock frequency of the system
552counter, which is provided by the platform.
553
554Platform initialization
555^^^^^^^^^^^^^^^^^^^^^^^
556
557BL31 performs detailed platform initialization, which enables normal world
558software to function correctly.
559
Dan Handley610e7e12018-03-01 18:44:00 +0000560On Arm platforms, this consists of the following:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100561
562- Initialize the console.
563- Configure the Interconnect to enable hardware coherency.
564- Enable the MMU and map the memory it needs to access.
565- Initialize the generic interrupt controller.
566- Initialize the power controller device.
567- Detect the system topology.
568
569Runtime services initialization
570^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
571
572BL31 is responsible for initializing the runtime services. One of them is PSCI.
573
574As part of the PSCI initializations, BL31 detects the system topology. It also
575initializes the data structures that implement the state machine used to track
576the state of power domain nodes. The state can be one of ``OFF``, ``RUN`` or
577``RETENTION``. All secondary CPUs are initially in the ``OFF`` state. The cluster
578that the primary CPU belongs to is ``ON``; any other cluster is ``OFF``. It also
579initializes the locks that protect them. BL31 accesses the state of a CPU or
580cluster immediately after reset and before the data cache is enabled in the
581warm boot path. It is not currently possible to use 'exclusive' based spinlocks,
582therefore BL31 uses locks based on Lamport's Bakery algorithm instead.
583
584The runtime service framework and its initialization is described in more
585detail in the "EL3 runtime services framework" section below.
586
587Details about the status of the PSCI implementation are provided in the
588"Power State Coordination Interface" section below.
589
590AArch64 BL32 (Secure-EL1 Payload) image initialization
591^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
592
593If a BL32 image is present then there must be a matching Secure-EL1 Payload
594Dispatcher (SPD) service (see later for details). During initialization
595that service must register a function to carry out initialization of BL32
596once the runtime services are fully initialized. BL31 invokes such a
597registered function to initialize BL32 before running BL33. This initialization
598is not necessary for AArch32 SPs.
599
600Details on BL32 initialization and the SPD's role are described in the
601"Secure-EL1 Payloads and Dispatchers" section below.
602
603BL33 (Non-trusted Firmware) execution
604^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
605
606EL3 Runtime Software initializes the EL2 or EL1 processor context for normal-
607world cold boot, ensuring that no secure state information finds its way into
608the non-secure execution state. EL3 Runtime Software uses the entrypoint
609information provided by BL2 to jump to the Non-trusted firmware image (BL33)
610at the highest available Exception Level (EL2 if available, otherwise EL1).
611
612Using alternative Trusted Boot Firmware in place of BL1 & BL2 (AArch64 only)
613~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
614
615Some platforms have existing implementations of Trusted Boot Firmware that
Dan Handley610e7e12018-03-01 18:44:00 +0000616would like to use TF-A BL31 for the EL3 Runtime Software. To enable this
617firmware architecture it is important to provide a fully documented and stable
618interface between the Trusted Boot Firmware and BL31.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100619
620Future changes to the BL31 interface will be done in a backwards compatible
621way, and this enables these firmware components to be independently enhanced/
622updated to develop and exploit new functionality.
623
624Required CPU state when calling ``bl31_entrypoint()`` during cold boot
625^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
626
627This function must only be called by the primary CPU.
628
629On entry to this function the calling primary CPU must be executing in AArch64
630EL3, little-endian data access, and all interrupt sources masked:
631
632::
633
634 PSTATE.EL = 3
635 PSTATE.RW = 1
636 PSTATE.DAIF = 0xf
637 SCTLR_EL3.EE = 0
638
639X0 and X1 can be used to pass information from the Trusted Boot Firmware to the
640platform code in BL31:
641
642::
643
Dan Handley610e7e12018-03-01 18:44:00 +0000644 X0 : Reserved for common TF-A information
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100645 X1 : Platform specific information
646
647BL31 zero-init sections (e.g. ``.bss``) should not contain valid data on entry,
648these will be zero filled prior to invoking platform setup code.
649
650Use of the X0 and X1 parameters
651'''''''''''''''''''''''''''''''
652
653The parameters are platform specific and passed from ``bl31_entrypoint()`` to
654``bl31_early_platform_setup()``. The value of these parameters is never directly
655used by the common BL31 code.
656
657The convention is that ``X0`` conveys information regarding the BL31, BL32 and
658BL33 images from the Trusted Boot firmware and ``X1`` can be used for other
Dan Handley610e7e12018-03-01 18:44:00 +0000659platform specific purpose. This convention allows platforms which use TF-A's
660BL1 and BL2 images to transfer additional platform specific information from
661Secure Boot without conflicting with future evolution of TF-A using ``X0`` to
662pass a ``bl31_params`` structure.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100663
664BL31 common and SPD initialization code depends on image and entrypoint
665information about BL33 and BL32, which is provided via BL31 platform APIs.
666This information is required until the start of execution of BL33. This
667information can be provided in a platform defined manner, e.g. compiled into
668the platform code in BL31, or provided in a platform defined memory location
669by the Trusted Boot firmware, or passed from the Trusted Boot Firmware via the
670Cold boot Initialization parameters. This data may need to be cleaned out of
671the CPU caches if it is provided by an earlier boot stage and then accessed by
672BL31 platform code before the caches are enabled.
673
Dan Handley610e7e12018-03-01 18:44:00 +0000674TF-A's BL2 implementation passes a ``bl31_params`` structure in
675``X0`` and the Arm development platforms interpret this in the BL31 platform
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100676code.
677
678MMU, Data caches & Coherency
679''''''''''''''''''''''''''''
680
681BL31 does not depend on the enabled state of the MMU, data caches or
682interconnect coherency on entry to ``bl31_entrypoint()``. If these are disabled
683on entry, these should be enabled during ``bl31_plat_arch_setup()``.
684
685Data structures used in the BL31 cold boot interface
686''''''''''''''''''''''''''''''''''''''''''''''''''''
687
688These structures are designed to support compatibility and independent
689evolution of the structures and the firmware images. For example, a version of
690BL31 that can interpret the BL3x image information from different versions of
691BL2, a platform that uses an extended entry\_point\_info structure to convey
692additional register information to BL31, or a ELF image loader that can convey
693more details about the firmware images.
694
695To support these scenarios the structures are versioned and sized, which enables
696BL31 to detect which information is present and respond appropriately. The
697``param_header`` is defined to capture this information:
698
699.. code:: c
700
701 typedef struct param_header {
702 uint8_t type; /* type of the structure */
703 uint8_t version; /* version of this structure */
704 uint16_t size; /* size of this structure in bytes */
705 uint32_t attr; /* attributes: unused bits SBZ */
706 } param_header_t;
707
708The structures using this format are ``entry_point_info``, ``image_info`` and
709``bl31_params``. The code that allocates and populates these structures must set
710the header fields appropriately, and the ``SET_PARAM_HEAD()`` a macro is defined
711to simplify this action.
712
713Required CPU state for BL31 Warm boot initialization
714^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
715
Dan Handley610e7e12018-03-01 18:44:00 +0000716When requesting a CPU power-on, or suspending a running CPU, TF-A provides
717the platform power management code with a Warm boot initialization
718entry-point, to be invoked by the CPU immediately after the reset handler.
719On entry to the Warm boot initialization function the calling CPU must be in
720AArch64 EL3, little-endian data access and all interrupt sources masked:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100721
722::
723
724 PSTATE.EL = 3
725 PSTATE.RW = 1
726 PSTATE.DAIF = 0xf
727 SCTLR_EL3.EE = 0
728
729The PSCI implementation will initialize the processor state and ensure that the
730platform power management code is then invoked as required to initialize all
731necessary system, cluster and CPU resources.
732
733AArch32 EL3 Runtime Software entrypoint interface
734~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
735
736To enable this firmware architecture it is important to provide a fully
737documented and stable interface between the Trusted Boot Firmware and the
738AArch32 EL3 Runtime Software.
739
740Future changes to the entrypoint interface will be done in a backwards
741compatible way, and this enables these firmware components to be independently
742enhanced/updated to develop and exploit new functionality.
743
744Required CPU state when entering during cold boot
745^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
746
747This function must only be called by the primary CPU.
748
749On entry to this function the calling primary CPU must be executing in AArch32
750EL3, little-endian data access, and all interrupt sources masked:
751
752::
753
754 PSTATE.AIF = 0x7
755 SCTLR.EE = 0
756
757R0 and R1 are used to pass information from the Trusted Boot Firmware to the
758platform code in AArch32 EL3 Runtime Software:
759
760::
761
Dan Handley610e7e12018-03-01 18:44:00 +0000762 R0 : Reserved for common TF-A information
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100763 R1 : Platform specific information
764
765Use of the R0 and R1 parameters
766'''''''''''''''''''''''''''''''
767
768The parameters are platform specific and the convention is that ``R0`` conveys
769information regarding the BL3x images from the Trusted Boot firmware and ``R1``
770can be used for other platform specific purpose. This convention allows
Dan Handley610e7e12018-03-01 18:44:00 +0000771platforms which use TF-A's BL1 and BL2 images to transfer additional platform
772specific information from Secure Boot without conflicting with future
773evolution of TF-A using ``R0`` to pass a ``bl_params`` structure.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100774
775The AArch32 EL3 Runtime Software is responsible for entry into BL33. This
776information can be obtained in a platform defined manner, e.g. compiled into
777the AArch32 EL3 Runtime Software, or provided in a platform defined memory
778location by the Trusted Boot firmware, or passed from the Trusted Boot Firmware
779via the Cold boot Initialization parameters. This data may need to be cleaned
780out of the CPU caches if it is provided by an earlier boot stage and then
781accessed by AArch32 EL3 Runtime Software before the caches are enabled.
782
Dan Handley610e7e12018-03-01 18:44:00 +0000783When using AArch32 EL3 Runtime Software, the Arm development platforms pass a
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100784``bl_params`` structure in ``R0`` from BL2 to be interpreted by AArch32 EL3 Runtime
785Software platform code.
786
787MMU, Data caches & Coherency
788''''''''''''''''''''''''''''
789
790AArch32 EL3 Runtime Software must not depend on the enabled state of the MMU,
791data caches or interconnect coherency in its entrypoint. They must be explicitly
792enabled if required.
793
794Data structures used in cold boot interface
795'''''''''''''''''''''''''''''''''''''''''''
796
797The AArch32 EL3 Runtime Software cold boot interface uses ``bl_params`` instead
798of ``bl31_params``. The ``bl_params`` structure is based on the convention
799described in AArch64 BL31 cold boot interface section.
800
801Required CPU state for warm boot initialization
802^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
803
804When requesting a CPU power-on, or suspending a running CPU, AArch32 EL3
805Runtime Software must ensure execution of a warm boot initialization entrypoint.
Dan Handley610e7e12018-03-01 18:44:00 +0000806If TF-A BL1 is used and the PROGRAMMABLE\_RESET\_ADDRESS build flag is false,
807then AArch32 EL3 Runtime Software must ensure that BL1 branches to the warm
808boot entrypoint by arranging for the BL1 platform function,
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100809plat\_get\_my\_entrypoint(), to return a non-zero value.
810
811In this case, the warm boot entrypoint must be in AArch32 EL3, little-endian
812data access and all interrupt sources masked:
813
814::
815
816 PSTATE.AIF = 0x7
817 SCTLR.EE = 0
818
Dan Handley610e7e12018-03-01 18:44:00 +0000819The warm boot entrypoint may be implemented by using TF-A
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100820``psci_warmboot_entrypoint()`` function. In that case, the platform must fulfil
821the pre-requisites mentioned in the `PSCI Library integration guide`_.
822
823EL3 runtime services framework
824------------------------------
825
826Software executing in the non-secure state and in the secure state at exception
827levels lower than EL3 will request runtime services using the Secure Monitor
828Call (SMC) instruction. These requests will follow the convention described in
829the SMC Calling Convention PDD (`SMCCC`_). The `SMCCC`_ assigns function
830identifiers to each SMC request and describes how arguments are passed and
831returned.
832
833The EL3 runtime services framework enables the development of services by
834different providers that can be easily integrated into final product firmware.
835The following sections describe the framework which facilitates the
836registration, initialization and use of runtime services in EL3 Runtime
837Software (BL31).
838
839The design of the runtime services depends heavily on the concepts and
840definitions described in the `SMCCC`_, in particular SMC Function IDs, Owning
841Entity Numbers (OEN), Fast and Yielding calls, and the SMC32 and SMC64 calling
842conventions. Please refer to that document for more detailed explanation of
843these terms.
844
845The following runtime services are expected to be implemented first. They have
846not all been instantiated in the current implementation.
847
848#. Standard service calls
849
850 This service is for management of the entire system. The Power State
851 Coordination Interface (`PSCI`_) is the first set of standard service calls
Dan Handley610e7e12018-03-01 18:44:00 +0000852 defined by Arm (see PSCI section later).
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100853
854#. Secure-EL1 Payload Dispatcher service
855
856 If a system runs a Trusted OS or other Secure-EL1 Payload (SP) then
857 it also requires a *Secure Monitor* at EL3 to switch the EL1 processor
858 context between the normal world (EL1/EL2) and trusted world (Secure-EL1).
859 The Secure Monitor will make these world switches in response to SMCs. The
860 `SMCCC`_ provides for such SMCs with the Trusted OS Call and Trusted
861 Application Call OEN ranges.
862
863 The interface between the EL3 Runtime Software and the Secure-EL1 Payload is
864 not defined by the `SMCCC`_ or any other standard. As a result, each
865 Secure-EL1 Payload requires a specific Secure Monitor that runs as a runtime
Dan Handley610e7e12018-03-01 18:44:00 +0000866 service - within TF-A this service is referred to as the Secure-EL1 Payload
867 Dispatcher (SPD).
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100868
Dan Handley610e7e12018-03-01 18:44:00 +0000869 TF-A provides a Test Secure-EL1 Payload (TSP) and its associated Dispatcher
870 (TSPD). Details of SPD design and TSP/TSPD operation are described in the
871 "Secure-EL1 Payloads and Dispatchers" section below.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100872
873#. CPU implementation service
874
875 This service will provide an interface to CPU implementation specific
876 services for a given platform e.g. access to processor errata workarounds.
877 This service is currently unimplemented.
878
Dan Handley610e7e12018-03-01 18:44:00 +0000879Additional services for Arm Architecture, SiP and OEM calls can be implemented.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100880Each implemented service handles a range of SMC function identifiers as
881described in the `SMCCC`_.
882
883Registration
884~~~~~~~~~~~~
885
886A runtime service is registered using the ``DECLARE_RT_SVC()`` macro, specifying
887the name of the service, the range of OENs covered, the type of service and
888initialization and call handler functions. This macro instantiates a ``const struct rt_svc_desc`` for the service with these details (see ``runtime_svc.h``).
889This structure is allocated in a special ELF section ``rt_svc_descs``, enabling
890the framework to find all service descriptors included into BL31.
891
892The specific service for a SMC Function is selected based on the OEN and call
893type of the Function ID, and the framework uses that information in the service
894descriptor to identify the handler for the SMC Call.
895
896The service descriptors do not include information to identify the precise set
897of SMC function identifiers supported by this service implementation, the
898security state from which such calls are valid nor the capability to support
89964-bit and/or 32-bit callers (using SMC32 or SMC64). Responding appropriately
900to these aspects of a SMC call is the responsibility of the service
901implementation, the framework is focused on integration of services from
902different providers and minimizing the time taken by the framework before the
903service handler is invoked.
904
905Details of the parameters, requirements and behavior of the initialization and
906call handling functions are provided in the following sections.
907
908Initialization
909~~~~~~~~~~~~~~
910
911``runtime_svc_init()`` in ``runtime_svc.c`` initializes the runtime services
912framework running on the primary CPU during cold boot as part of the BL31
913initialization. This happens prior to initializing a Trusted OS and running
914Normal world boot firmware that might in turn use these services.
915Initialization involves validating each of the declared runtime service
916descriptors, calling the service initialization function and populating the
917index used for runtime lookup of the service.
918
919The BL31 linker script collects all of the declared service descriptors into a
920single array and defines symbols that allow the framework to locate and traverse
921the array, and determine its size.
922
923The framework does basic validation of each descriptor to halt firmware
924initialization if service declaration errors are detected. The framework does
925not check descriptors for the following error conditions, and may behave in an
926unpredictable manner under such scenarios:
927
928#. Overlapping OEN ranges
929#. Multiple descriptors for the same range of OENs and ``call_type``
930#. Incorrect range of owning entity numbers for a given ``call_type``
931
932Once validated, the service ``init()`` callback is invoked. This function carries
933out any essential EL3 initialization before servicing requests. The ``init()``
934function is only invoked on the primary CPU during cold boot. If the service
935uses per-CPU data this must either be initialized for all CPUs during this call,
936or be done lazily when a CPU first issues an SMC call to that service. If
937``init()`` returns anything other than ``0``, this is treated as an initialization
938error and the service is ignored: this does not cause the firmware to halt.
939
940The OEN and call type fields present in the SMC Function ID cover a total of
941128 distinct services, but in practice a single descriptor can cover a range of
942OENs, e.g. SMCs to call a Trusted OS function. To optimize the lookup of a
943service handler, the framework uses an array of 128 indices that map every
944distinct OEN/call-type combination either to one of the declared services or to
945indicate the service is not handled. This ``rt_svc_descs_indices[]`` array is
946populated for all of the OENs covered by a service after the service ``init()``
947function has reported success. So a service that fails to initialize will never
948have it's ``handle()`` function invoked.
949
950The following figure shows how the ``rt_svc_descs_indices[]`` index maps the SMC
951Function ID call type and OEN onto a specific service handler in the
952``rt_svc_descs[]`` array.
953
954|Image 1|
955
956Handling an SMC
957~~~~~~~~~~~~~~~
958
959When the EL3 runtime services framework receives a Secure Monitor Call, the SMC
960Function ID is passed in W0 from the lower exception level (as per the
961`SMCCC`_). If the calling register width is AArch32, it is invalid to invoke an
962SMC Function which indicates the SMC64 calling convention: such calls are
963ignored and return the Unknown SMC Function Identifier result code ``0xFFFFFFFF``
964in R0/X0.
965
966Bit[31] (fast/yielding call) and bits[29:24] (owning entity number) of the SMC
967Function ID are combined to index into the ``rt_svc_descs_indices[]`` array. The
968resulting value might indicate a service that has no handler, in this case the
969framework will also report an Unknown SMC Function ID. Otherwise, the value is
970used as a further index into the ``rt_svc_descs[]`` array to locate the required
971service and handler.
972
973The service's ``handle()`` callback is provided with five of the SMC parameters
974directly, the others are saved into memory for retrieval (if needed) by the
975handler. The handler is also provided with an opaque ``handle`` for use with the
976supporting library for parameter retrieval, setting return values and context
977manipulation; and with ``flags`` indicating the security state of the caller. The
978framework finally sets up the execution stack for the handler, and invokes the
979services ``handle()`` function.
980
981On return from the handler the result registers are populated in X0-X3 before
982restoring the stack and CPU state and returning from the original SMC.
983
984Power State Coordination Interface
985----------------------------------
986
987TODO: Provide design walkthrough of PSCI implementation.
988
Roberto Vargasd963e3e2017-09-12 10:28:35 +0100989The PSCI v1.1 specification categorizes APIs as optional and mandatory. All the
990mandatory APIs in PSCI v1.1, PSCI v1.0 and in PSCI v0.2 draft specification
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100991`Power State Coordination Interface PDD`_ are implemented. The table lists
Roberto Vargasd963e3e2017-09-12 10:28:35 +0100992the PSCI v1.1 APIs and their support in generic code.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100993
994An API implementation might have a dependency on platform code e.g. CPU\_SUSPEND
995requires the platform to export a part of the implementation. Hence the level
996of support of the mandatory APIs depends upon the support exported by the
997platform port as well. The Juno and FVP (all variants) platforms export all the
998required support.
999
1000+-----------------------------+-------------+-------------------------------+
Roberto Vargasd963e3e2017-09-12 10:28:35 +01001001| PSCI v1.1 API | Supported | Comments |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001002+=============================+=============+===============================+
Roberto Vargasd963e3e2017-09-12 10:28:35 +01001003| ``PSCI_VERSION`` | Yes | The version returned is 1.1 |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001004+-----------------------------+-------------+-------------------------------+
1005| ``CPU_SUSPEND`` | Yes\* | |
1006+-----------------------------+-------------+-------------------------------+
1007| ``CPU_OFF`` | Yes\* | |
1008+-----------------------------+-------------+-------------------------------+
1009| ``CPU_ON`` | Yes\* | |
1010+-----------------------------+-------------+-------------------------------+
1011| ``AFFINITY_INFO`` | Yes | |
1012+-----------------------------+-------------+-------------------------------+
1013| ``MIGRATE`` | Yes\*\* | |
1014+-----------------------------+-------------+-------------------------------+
1015| ``MIGRATE_INFO_TYPE`` | Yes\*\* | |
1016+-----------------------------+-------------+-------------------------------+
1017| ``MIGRATE_INFO_CPU`` | Yes\*\* | |
1018+-----------------------------+-------------+-------------------------------+
1019| ``SYSTEM_OFF`` | Yes\* | |
1020+-----------------------------+-------------+-------------------------------+
1021| ``SYSTEM_RESET`` | Yes\* | |
1022+-----------------------------+-------------+-------------------------------+
1023| ``PSCI_FEATURES`` | Yes | |
1024+-----------------------------+-------------+-------------------------------+
1025| ``CPU_FREEZE`` | No | |
1026+-----------------------------+-------------+-------------------------------+
1027| ``CPU_DEFAULT_SUSPEND`` | No | |
1028+-----------------------------+-------------+-------------------------------+
1029| ``NODE_HW_STATE`` | Yes\* | |
1030+-----------------------------+-------------+-------------------------------+
1031| ``SYSTEM_SUSPEND`` | Yes\* | |
1032+-----------------------------+-------------+-------------------------------+
1033| ``PSCI_SET_SUSPEND_MODE`` | No | |
1034+-----------------------------+-------------+-------------------------------+
1035| ``PSCI_STAT_RESIDENCY`` | Yes\* | |
1036+-----------------------------+-------------+-------------------------------+
1037| ``PSCI_STAT_COUNT`` | Yes\* | |
1038+-----------------------------+-------------+-------------------------------+
Roberto Vargasd963e3e2017-09-12 10:28:35 +01001039| ``SYSTEM_RESET2`` | Yes\* | |
1040+-----------------------------+-------------+-------------------------------+
1041| ``MEM_PROTECT`` | Yes\* | |
1042+-----------------------------+-------------+-------------------------------+
1043| ``MEM_PROTECT_CHECK_RANGE`` | Yes\* | |
1044+-----------------------------+-------------+-------------------------------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001045
1046\*Note : These PSCI APIs require platform power management hooks to be
1047registered with the generic PSCI code to be supported.
1048
1049\*\*Note : These PSCI APIs require appropriate Secure Payload Dispatcher
1050hooks to be registered with the generic PSCI code to be supported.
1051
Dan Handley610e7e12018-03-01 18:44:00 +00001052The PSCI implementation in TF-A is a library which can be integrated with
1053AArch64 or AArch32 EL3 Runtime Software for Armv8-A systems. A guide to
1054integrating PSCI library with AArch32 EL3 Runtime Software can be found
1055`here`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001056
1057Secure-EL1 Payloads and Dispatchers
1058-----------------------------------
1059
1060On a production system that includes a Trusted OS running in Secure-EL1/EL0,
1061the Trusted OS is coupled with a companion runtime service in the BL31
1062firmware. This service is responsible for the initialisation of the Trusted
1063OS and all communications with it. The Trusted OS is the BL32 stage of the
Dan Handley610e7e12018-03-01 18:44:00 +00001064boot flow in TF-A. The firmware will attempt to locate, load and execute a
1065BL32 image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001066
Dan Handley610e7e12018-03-01 18:44:00 +00001067TF-A uses a more general term for the BL32 software that runs at Secure-EL1 -
1068the *Secure-EL1 Payload* - as it is not always a Trusted OS.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001069
Dan Handley610e7e12018-03-01 18:44:00 +00001070TF-A provides a Test Secure-EL1 Payload (TSP) and a Test Secure-EL1 Payload
1071Dispatcher (TSPD) service as an example of how a Trusted OS is supported on a
1072production system using the Runtime Services Framework. On such a system, the
1073Test BL32 image and service are replaced by the Trusted OS and its dispatcher
1074service. The TF-A build system expects that the dispatcher will define the
1075build flag ``NEED_BL32`` to enable it to include the BL32 in the build either
1076as a binary or to compile from source depending on whether the ``BL32`` build
1077option is specified or not.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001078
1079The TSP runs in Secure-EL1. It is designed to demonstrate synchronous
1080communication with the normal-world software running in EL1/EL2. Communication
1081is initiated by the normal-world software
1082
1083- either directly through a Fast SMC (as defined in the `SMCCC`_)
1084
1085- or indirectly through a `PSCI`_ SMC. The `PSCI`_ implementation in turn
1086 informs the TSPD about the requested power management operation. This allows
1087 the TSP to prepare for or respond to the power state change
1088
1089The TSPD service is responsible for.
1090
1091- Initializing the TSP
1092
1093- Routing requests and responses between the secure and the non-secure
1094 states during the two types of communications just described
1095
1096Initializing a BL32 Image
1097~~~~~~~~~~~~~~~~~~~~~~~~~
1098
1099The Secure-EL1 Payload Dispatcher (SPD) service is responsible for initializing
1100the BL32 image. It needs access to the information passed by BL2 to BL31 to do
1101so. This is provided by:
1102
1103.. code:: c
1104
1105 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t);
1106
1107which returns a reference to the ``entry_point_info`` structure corresponding to
1108the image which will be run in the specified security state. The SPD uses this
1109API to get entry point information for the SECURE image, BL32.
1110
1111In the absence of a BL32 image, BL31 passes control to the normal world
1112bootloader image (BL33). When the BL32 image is present, it is typical
1113that the SPD wants control to be passed to BL32 first and then later to BL33.
1114
1115To do this the SPD has to register a BL32 initialization function during
1116initialization of the SPD service. The BL32 initialization function has this
1117prototype:
1118
1119.. code:: c
1120
1121 int32_t init(void);
1122
1123and is registered using the ``bl31_register_bl32_init()`` function.
1124
Dan Handley610e7e12018-03-01 18:44:00 +00001125TF-A supports two approaches for the SPD to pass control to BL32 before
1126returning through EL3 and running the non-trusted firmware (BL33):
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001127
1128#. In the BL32 setup function, use ``bl31_set_next_image_type()`` to
1129 request that the exit from ``bl31_main()`` is to the BL32 entrypoint in
1130 Secure-EL1. BL31 will exit to BL32 using the asynchronous method by
1131 calling ``bl31_prepare_next_image_entry()`` and ``el3_exit()``.
1132
1133 When the BL32 has completed initialization at Secure-EL1, it returns to
1134 BL31 by issuing an SMC, using a Function ID allocated to the SPD. On
1135 receipt of this SMC, the SPD service handler should switch the CPU context
1136 from trusted to normal world and use the ``bl31_set_next_image_type()`` and
1137 ``bl31_prepare_next_image_entry()`` functions to set up the initial return to
1138 the normal world firmware BL33. On return from the handler the framework
1139 will exit to EL2 and run BL33.
1140
1141#. The BL32 setup function registers an initialization function using
1142 ``bl31_register_bl32_init()`` which provides a SPD-defined mechanism to
1143 invoke a 'world-switch synchronous call' to Secure-EL1 to run the BL32
1144 entrypoint.
Dan Handley610e7e12018-03-01 18:44:00 +00001145 NOTE: The Test SPD service included with TF-A provides one implementation
1146 of such a mechanism.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001147
1148 On completion BL32 returns control to BL31 via a SMC, and on receipt the
1149 SPD service handler invokes the synchronous call return mechanism to return
1150 to the BL32 initialization function. On return from this function,
1151 ``bl31_main()`` will set up the return to the normal world firmware BL33 and
1152 continue the boot process in the normal world.
1153
Jeenu Viswambharanb60420a2017-08-24 15:43:44 +01001154Crash Reporting in BL31
1155-----------------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001156
1157BL31 implements a scheme for reporting the processor state when an unhandled
1158exception is encountered. The reporting mechanism attempts to preserve all the
1159register contents and report it via a dedicated UART (PL011 console). BL31
1160reports the general purpose, EL3, Secure EL1 and some EL2 state registers.
1161
1162A dedicated per-CPU crash stack is maintained by BL31 and this is retrieved via
1163the per-CPU pointer cache. The implementation attempts to minimise the memory
1164required for this feature. The file ``crash_reporting.S`` contains the
1165implementation for crash reporting.
1166
1167The sample crash output is shown below.
1168
1169::
1170
1171 x0 :0x000000004F00007C
1172 x1 :0x0000000007FFFFFF
1173 x2 :0x0000000004014D50
1174 x3 :0x0000000000000000
1175 x4 :0x0000000088007998
1176 x5 :0x00000000001343AC
1177 x6 :0x0000000000000016
1178 x7 :0x00000000000B8A38
1179 x8 :0x00000000001343AC
1180 x9 :0x00000000000101A8
1181 x10 :0x0000000000000002
1182 x11 :0x000000000000011C
1183 x12 :0x00000000FEFDC644
1184 x13 :0x00000000FED93FFC
1185 x14 :0x0000000000247950
1186 x15 :0x00000000000007A2
1187 x16 :0x00000000000007A4
1188 x17 :0x0000000000247950
1189 x18 :0x0000000000000000
1190 x19 :0x00000000FFFFFFFF
1191 x20 :0x0000000004014D50
1192 x21 :0x000000000400A38C
1193 x22 :0x0000000000247950
1194 x23 :0x0000000000000010
1195 x24 :0x0000000000000024
1196 x25 :0x00000000FEFDC868
1197 x26 :0x00000000FEFDC86A
1198 x27 :0x00000000019EDEDC
1199 x28 :0x000000000A7CFDAA
1200 x29 :0x0000000004010780
1201 x30 :0x000000000400F004
1202 scr_el3 :0x0000000000000D3D
1203 sctlr_el3 :0x0000000000C8181F
1204 cptr_el3 :0x0000000000000000
1205 tcr_el3 :0x0000000080803520
1206 daif :0x00000000000003C0
1207 mair_el3 :0x00000000000004FF
1208 spsr_el3 :0x00000000800003CC
1209 elr_el3 :0x000000000400C0CC
1210 ttbr0_el3 :0x00000000040172A0
1211 esr_el3 :0x0000000096000210
1212 sp_el3 :0x0000000004014D50
1213 far_el3 :0x000000004F00007C
1214 spsr_el1 :0x0000000000000000
1215 elr_el1 :0x0000000000000000
1216 spsr_abt :0x0000000000000000
1217 spsr_und :0x0000000000000000
1218 spsr_irq :0x0000000000000000
1219 spsr_fiq :0x0000000000000000
1220 sctlr_el1 :0x0000000030C81807
1221 actlr_el1 :0x0000000000000000
1222 cpacr_el1 :0x0000000000300000
1223 csselr_el1 :0x0000000000000002
1224 sp_el1 :0x0000000004028800
1225 esr_el1 :0x0000000000000000
1226 ttbr0_el1 :0x000000000402C200
1227 ttbr1_el1 :0x0000000000000000
1228 mair_el1 :0x00000000000004FF
1229 amair_el1 :0x0000000000000000
1230 tcr_el1 :0x0000000000003520
1231 tpidr_el1 :0x0000000000000000
1232 tpidr_el0 :0x0000000000000000
1233 tpidrro_el0 :0x0000000000000000
1234 dacr32_el2 :0x0000000000000000
1235 ifsr32_el2 :0x0000000000000000
1236 par_el1 :0x0000000000000000
1237 far_el1 :0x0000000000000000
1238 afsr0_el1 :0x0000000000000000
1239 afsr1_el1 :0x0000000000000000
1240 contextidr_el1 :0x0000000000000000
1241 vbar_el1 :0x0000000004027000
1242 cntp_ctl_el0 :0x0000000000000000
1243 cntp_cval_el0 :0x0000000000000000
1244 cntv_ctl_el0 :0x0000000000000000
1245 cntv_cval_el0 :0x0000000000000000
1246 cntkctl_el1 :0x0000000000000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001247 sp_el0 :0x0000000004010780
1248
1249Guidelines for Reset Handlers
1250-----------------------------
1251
Dan Handley610e7e12018-03-01 18:44:00 +00001252TF-A implements a framework that allows CPU and platform ports to perform
1253actions very early after a CPU is released from reset in both the cold and warm
1254boot paths. This is done by calling the ``reset_handler()`` function in both
1255the BL1 and BL31 images. It in turn calls the platform and CPU specific reset
1256handling functions.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001257
1258Details for implementing a CPU specific reset handler can be found in
1259Section 8. Details for implementing a platform specific reset handler can be
1260found in the `Porting Guide`_ (see the ``plat_reset_handler()`` function).
1261
1262When adding functionality to a reset handler, keep in mind that if a different
1263reset handling behavior is required between the first and the subsequent
1264invocations of the reset handling code, this should be detected at runtime.
1265In other words, the reset handler should be able to detect whether an action has
1266already been performed and act as appropriate. Possible courses of actions are,
1267e.g. skip the action the second time, or undo/redo it.
1268
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +01001269Configuring secure interrupts
1270-----------------------------
1271
1272The GIC driver is responsible for performing initial configuration of secure
1273interrupts on the platform. To this end, the platform is expected to provide the
1274GIC driver (either GICv2 or GICv3, as selected by the platform) with the
1275interrupt configuration during the driver initialisation.
1276
Antonio Nino Diaz29b9f5b2018-09-24 17:23:24 +01001277Secure interrupt configuration are specified in an array of secure interrupt
1278properties. In this scheme, in both GICv2 and GICv3 driver data structures, the
1279``interrupt_props`` member points to an array of interrupt properties. Each
1280element of the array specifies the interrupt number and its configuration, viz.
1281priority, group, configuration. Each element of the array shall be populated by
1282the macro ``INTR_PROP_DESC()``. The macro takes the following arguments:
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +01001283
Antonio Nino Diaz29b9f5b2018-09-24 17:23:24 +01001284- 10-bit interrupt number,
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +01001285
Antonio Nino Diaz29b9f5b2018-09-24 17:23:24 +01001286- 8-bit interrupt priority,
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +01001287
Antonio Nino Diaz29b9f5b2018-09-24 17:23:24 +01001288- Interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1``,
1289 ``INTR_TYPE_NS``),
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +01001290
Antonio Nino Diaz29b9f5b2018-09-24 17:23:24 +01001291- Interrupt configuration (either ``GIC_INTR_CFG_LEVEL`` or
1292 ``GIC_INTR_CFG_EDGE``).
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +01001293
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001294CPU specific operations framework
1295---------------------------------
1296
Dan Handley610e7e12018-03-01 18:44:00 +00001297Certain aspects of the Armv8-A architecture are implementation defined,
1298that is, certain behaviours are not architecturally defined, but must be
1299defined and documented by individual processor implementations. TF-A
1300implements a framework which categorises the common implementation defined
1301behaviours and allows a processor to export its implementation of that
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001302behaviour. The categories are:
1303
1304#. Processor specific reset sequence.
1305
1306#. Processor specific power down sequences.
1307
1308#. Processor specific register dumping as a part of crash reporting.
1309
1310#. Errata status reporting.
1311
1312Each of the above categories fulfils a different requirement.
1313
1314#. allows any processor specific initialization before the caches and MMU
1315 are turned on, like implementation of errata workarounds, entry into
1316 the intra-cluster coherency domain etc.
1317
1318#. allows each processor to implement the power down sequence mandated in
1319 its Technical Reference Manual (TRM).
1320
1321#. allows a processor to provide additional information to the developer
1322 in the event of a crash, for example Cortex-A53 has registers which
1323 can expose the data cache contents.
1324
1325#. allows a processor to define a function that inspects and reports the status
1326 of all errata workarounds on that processor.
1327
1328Please note that only 2. is mandated by the TRM.
1329
1330The CPU specific operations framework scales to accommodate a large number of
1331different CPUs during power down and reset handling. The platform can specify
1332any CPU optimization it wants to enable for each CPU. It can also specify
1333the CPU errata workarounds to be applied for each CPU type during reset
1334handling by defining CPU errata compile time macros. Details on these macros
1335can be found in the `cpu-specific-build-macros.rst`_ file.
1336
1337The CPU specific operations framework depends on the ``cpu_ops`` structure which
1338needs to be exported for each type of CPU in the platform. It is defined in
1339``include/lib/cpus/aarch64/cpu_macros.S`` and has the following fields : ``midr``,
1340``reset_func()``, ``cpu_pwr_down_ops`` (array of power down functions) and
1341``cpu_reg_dump()``.
1342
1343The CPU specific files in ``lib/cpus`` export a ``cpu_ops`` data structure with
1344suitable handlers for that CPU. For example, ``lib/cpus/aarch64/cortex_a53.S``
1345exports the ``cpu_ops`` for Cortex-A53 CPU. According to the platform
1346configuration, these CPU specific files must be included in the build by
1347the platform makefile. The generic CPU specific operations framework code exists
1348in ``lib/cpus/aarch64/cpu_helpers.S``.
1349
1350CPU specific Reset Handling
1351~~~~~~~~~~~~~~~~~~~~~~~~~~~
1352
1353After a reset, the state of the CPU when it calls generic reset handler is:
1354MMU turned off, both instruction and data caches turned off and not part
1355of any coherency domain.
1356
1357The BL entrypoint code first invokes the ``plat_reset_handler()`` to allow
1358the platform to perform any system initialization required and any system
1359errata workarounds that needs to be applied. The ``get_cpu_ops_ptr()`` reads
1360the current CPU midr, finds the matching ``cpu_ops`` entry in the ``cpu_ops``
1361array and returns it. Note that only the part number and implementer fields
1362in midr are used to find the matching ``cpu_ops`` entry. The ``reset_func()`` in
1363the returned ``cpu_ops`` is then invoked which executes the required reset
1364handling for that CPU and also any errata workarounds enabled by the platform.
1365This function must preserve the values of general purpose registers x20 to x29.
1366
1367Refer to Section "Guidelines for Reset Handlers" for general guidelines
1368regarding placement of code in a reset handler.
1369
1370CPU specific power down sequence
1371~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1372
1373During the BL31 initialization sequence, the pointer to the matching ``cpu_ops``
1374entry is stored in per-CPU data by ``init_cpu_ops()`` so that it can be quickly
1375retrieved during power down sequences.
1376
1377Various CPU drivers register handlers to perform power down at certain power
1378levels for that specific CPU. The PSCI service, upon receiving a power down
1379request, determines the highest power level at which to execute power down
1380sequence for a particular CPU. It uses the ``prepare_cpu_pwr_dwn()`` function to
1381pick the right power down handler for the requested level. The function
1382retrieves ``cpu_ops`` pointer member of per-CPU data, and from that, further
1383retrieves ``cpu_pwr_down_ops`` array, and indexes into the required level. If the
1384requested power level is higher than what a CPU driver supports, the handler
1385registered for highest level is invoked.
1386
1387At runtime the platform hooks for power down are invoked by the PSCI service to
1388perform platform specific operations during a power down sequence, for example
1389turning off CCI coherency during a cluster power down.
1390
1391CPU specific register reporting during crash
1392~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1393
1394If the crash reporting is enabled in BL31, when a crash occurs, the crash
1395reporting framework calls ``do_cpu_reg_dump`` which retrieves the matching
1396``cpu_ops`` using ``get_cpu_ops_ptr()`` function. The ``cpu_reg_dump()`` in
1397``cpu_ops`` is invoked, which then returns the CPU specific register values to
1398be reported and a pointer to the ASCII list of register names in a format
1399expected by the crash reporting framework.
1400
1401CPU errata status reporting
1402~~~~~~~~~~~~~~~~~~~~~~~~~~~
1403
Dan Handley610e7e12018-03-01 18:44:00 +00001404Errata workarounds for CPUs supported in TF-A are applied during both cold and
1405warm boots, shortly after reset. Individual Errata workarounds are enabled as
1406build options. Some errata workarounds have potential run-time implications;
1407therefore some are enabled by default, others not. Platform ports shall
1408override build options to enable or disable errata as appropriate. The CPU
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001409drivers take care of applying errata workarounds that are enabled and applicable
1410to a given CPU. Refer to the section titled *CPU Errata Workarounds* in `CPUBM`_
1411for more information.
1412
1413Functions in CPU drivers that apply errata workaround must follow the
1414conventions listed below.
1415
1416The errata workaround must be authored as two separate functions:
1417
1418- One that checks for errata. This function must determine whether that errata
1419 applies to the current CPU. Typically this involves matching the current
1420 CPUs revision and variant against a value that's known to be affected by the
1421 errata. If the function determines that the errata applies to this CPU, it
1422 must return ``ERRATA_APPLIES``; otherwise, it must return
1423 ``ERRATA_NOT_APPLIES``. The utility functions ``cpu_get_rev_var`` and
1424 ``cpu_rev_var_ls`` functions may come in handy for this purpose.
1425
1426For an errata identified as ``E``, the check function must be named
1427``check_errata_E``.
1428
1429This function will be invoked at different times, both from assembly and from
1430C run time. Therefore it must follow AAPCS, and must not use stack.
1431
1432- Another one that applies the errata workaround. This function would call the
1433 check function described above, and applies errata workaround if required.
1434
1435CPU drivers that apply errata workaround can optionally implement an assembly
1436function that report the status of errata workarounds pertaining to that CPU.
1437For a driver that registers the CPU, for example, ``cpux`` via. ``declare_cpu_ops``
1438macro, the errata reporting function, if it exists, must be named
1439``cpux_errata_report``. This function will always be called with MMU enabled; it
1440must follow AAPCS and may use stack.
1441
Dan Handley610e7e12018-03-01 18:44:00 +00001442In a debug build of TF-A, on a CPU that comes out of reset, both BL1 and the
1443runtime firmware (BL31 in AArch64, and BL32 in AArch32) will invoke errata
1444status reporting function, if one exists, for that type of CPU.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001445
1446To report the status of each errata workaround, the function shall use the
1447assembler macro ``report_errata``, passing it:
1448
1449- The build option that enables the errata;
1450
1451- The name of the CPU: this must be the same identifier that CPU driver
1452 registered itself with, using ``declare_cpu_ops``;
1453
1454- And the errata identifier: the identifier must match what's used in the
1455 errata's check function described above.
1456
1457The errata status reporting function will be called once per CPU type/errata
1458combination during the software's active life time.
1459
Dan Handley610e7e12018-03-01 18:44:00 +00001460It's expected that whenever an errata workaround is submitted to TF-A, the
1461errata reporting function is appropriately extended to report its status as
1462well.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001463
1464Reporting the status of errata workaround is for informational purpose only; it
1465has no functional significance.
1466
1467Memory layout of BL images
1468--------------------------
1469
1470Each bootloader image can be divided in 2 parts:
1471
1472- the static contents of the image. These are data actually stored in the
1473 binary on the disk. In the ELF terminology, they are called ``PROGBITS``
1474 sections;
1475
1476- the run-time contents of the image. These are data that don't occupy any
1477 space in the binary on the disk. The ELF binary just contains some
1478 metadata indicating where these data will be stored at run-time and the
1479 corresponding sections need to be allocated and initialized at run-time.
1480 In the ELF terminology, they are called ``NOBITS`` sections.
1481
1482All PROGBITS sections are grouped together at the beginning of the image,
Dan Handley610e7e12018-03-01 18:44:00 +00001483followed by all NOBITS sections. This is true for all TF-A images and it is
1484governed by the linker scripts. This ensures that the raw binary images are
1485as small as possible. If a NOBITS section was inserted in between PROGBITS
1486sections then the resulting binary file would contain zero bytes in place of
1487this NOBITS section, making the image unnecessarily bigger. Smaller images
1488allow faster loading from the FIP to the main memory.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001489
1490Linker scripts and symbols
1491~~~~~~~~~~~~~~~~~~~~~~~~~~
1492
1493Each bootloader stage image layout is described by its own linker script. The
1494linker scripts export some symbols into the program symbol table. Their values
Dan Handley610e7e12018-03-01 18:44:00 +00001495correspond to particular addresses. TF-A code can refer to these symbols to
1496figure out the image memory layout.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001497
Dan Handley610e7e12018-03-01 18:44:00 +00001498Linker symbols follow the following naming convention in TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001499
1500- ``__<SECTION>_START__``
1501
1502 Start address of a given section named ``<SECTION>``.
1503
1504- ``__<SECTION>_END__``
1505
1506 End address of a given section named ``<SECTION>``. If there is an alignment
1507 constraint on the section's end address then ``__<SECTION>_END__`` corresponds
1508 to the end address of the section's actual contents, rounded up to the right
1509 boundary. Refer to the value of ``__<SECTION>_UNALIGNED_END__`` to know the
1510 actual end address of the section's contents.
1511
1512- ``__<SECTION>_UNALIGNED_END__``
1513
1514 End address of a given section named ``<SECTION>`` without any padding or
1515 rounding up due to some alignment constraint.
1516
1517- ``__<SECTION>_SIZE__``
1518
1519 Size (in bytes) of a given section named ``<SECTION>``. If there is an
1520 alignment constraint on the section's end address then ``__<SECTION>_SIZE__``
1521 corresponds to the size of the section's actual contents, rounded up to the
1522 right boundary. In other words, ``__<SECTION>_SIZE__ = __<SECTION>_END__ - _<SECTION>_START__``. Refer to the value of ``__<SECTION>_UNALIGNED_SIZE__``
1523 to know the actual size of the section's contents.
1524
1525- ``__<SECTION>_UNALIGNED_SIZE__``
1526
1527 Size (in bytes) of a given section named ``<SECTION>`` without any padding or
1528 rounding up due to some alignment constraint. In other words,
1529 ``__<SECTION>_UNALIGNED_SIZE__ = __<SECTION>_UNALIGNED_END__ - __<SECTION>_START__``.
1530
Dan Handley610e7e12018-03-01 18:44:00 +00001531Some of the linker symbols are mandatory as TF-A code relies on them to be
1532defined. They are listed in the following subsections. Some of them must be
1533provided for each bootloader stage and some are specific to a given bootloader
1534stage.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001535
1536The linker scripts define some extra, optional symbols. They are not actually
1537used by any code but they help in understanding the bootloader images' memory
1538layout as they are easy to spot in the link map files.
1539
1540Common linker symbols
1541^^^^^^^^^^^^^^^^^^^^^
1542
1543All BL images share the following requirements:
1544
1545- The BSS section must be zero-initialised before executing any C code.
1546- The coherent memory section (if enabled) must be zero-initialised as well.
1547- The MMU setup code needs to know the extents of the coherent and read-only
1548 memory regions to set the right memory attributes. When
1549 ``SEPARATE_CODE_AND_RODATA=1``, it needs to know more specifically how the
1550 read-only memory region is divided between code and data.
1551
1552The following linker symbols are defined for this purpose:
1553
1554- ``__BSS_START__``
1555- ``__BSS_SIZE__``
1556- ``__COHERENT_RAM_START__`` Must be aligned on a page-size boundary.
1557- ``__COHERENT_RAM_END__`` Must be aligned on a page-size boundary.
1558- ``__COHERENT_RAM_UNALIGNED_SIZE__``
1559- ``__RO_START__``
1560- ``__RO_END__``
1561- ``__TEXT_START__``
1562- ``__TEXT_END__``
1563- ``__RODATA_START__``
1564- ``__RODATA_END__``
1565
1566BL1's linker symbols
1567^^^^^^^^^^^^^^^^^^^^
1568
1569BL1 being the ROM image, it has additional requirements. BL1 resides in ROM and
1570it is entirely executed in place but it needs some read-write memory for its
1571mutable data. Its ``.data`` section (i.e. its allocated read-write data) must be
1572relocated from ROM to RAM before executing any C code.
1573
1574The following additional linker symbols are defined for BL1:
1575
1576- ``__BL1_ROM_END__`` End address of BL1's ROM contents, covering its code
1577 and ``.data`` section in ROM.
1578- ``__DATA_ROM_START__`` Start address of the ``.data`` section in ROM. Must be
1579 aligned on a 16-byte boundary.
1580- ``__DATA_RAM_START__`` Address in RAM where the ``.data`` section should be
1581 copied over. Must be aligned on a 16-byte boundary.
1582- ``__DATA_SIZE__`` Size of the ``.data`` section (in ROM or RAM).
1583- ``__BL1_RAM_START__`` Start address of BL1 read-write data.
1584- ``__BL1_RAM_END__`` End address of BL1 read-write data.
1585
1586How to choose the right base addresses for each bootloader stage image
1587~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1588
Dan Handley610e7e12018-03-01 18:44:00 +00001589There is currently no support for dynamic image loading in TF-A. This means
1590that all bootloader images need to be linked against their ultimate runtime
1591locations and the base addresses of each image must be chosen carefully such
1592that images don't overlap each other in an undesired way. As the code grows,
1593the base addresses might need adjustments to cope with the new memory layout.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001594
1595The memory layout is completely specific to the platform and so there is no
1596general recipe for choosing the right base addresses for each bootloader image.
1597However, there are tools to aid in understanding the memory layout. These are
1598the link map files: ``build/<platform>/<build-type>/bl<x>/bl<x>.map``, with ``<x>``
1599being the stage bootloader. They provide a detailed view of the memory usage of
1600each image. Among other useful information, they provide the end address of
1601each image.
1602
1603- ``bl1.map`` link map file provides ``__BL1_RAM_END__`` address.
1604- ``bl2.map`` link map file provides ``__BL2_END__`` address.
1605- ``bl31.map`` link map file provides ``__BL31_END__`` address.
1606- ``bl32.map`` link map file provides ``__BL32_END__`` address.
1607
1608For each bootloader image, the platform code must provide its start address
1609as well as a limit address that it must not overstep. The latter is used in the
1610linker scripts to check that the image doesn't grow past that address. If that
1611happens, the linker will issue a message similar to the following:
1612
1613::
1614
1615 aarch64-none-elf-ld: BLx has exceeded its limit.
1616
1617Additionally, if the platform memory layout implies some image overlaying like
1618on FVP, BL31 and TSP need to know the limit address that their PROGBITS
1619sections must not overstep. The platform code must provide those.
1620
Soby Mathew97b1bff2018-09-27 16:46:41 +01001621TF-A does not provide any mechanism to verify at boot time that the memory
1622to load a new image is free to prevent overwriting a previously loaded image.
1623The platform must specify the memory available in the system for all the
1624relevant BL images to be loaded.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001625
1626For example, in the case of BL1 loading BL2, ``bl1_plat_sec_mem_layout()`` will
1627return the region defined by the platform where BL1 intends to load BL2. The
1628``load_image()`` function performs bounds check for the image size based on the
1629base and maximum image size provided by the platforms. Platforms must take
1630this behaviour into account when defining the base/size for each of the images.
1631
Dan Handley610e7e12018-03-01 18:44:00 +00001632Memory layout on Arm development platforms
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001633^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1634
Dan Handley610e7e12018-03-01 18:44:00 +00001635The following list describes the memory layout on the Arm development platforms:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001636
1637- A 4KB page of shared memory is used for communication between Trusted
1638 Firmware and the platform's power controller. This is located at the base of
1639 Trusted SRAM. The amount of Trusted SRAM available to load the bootloader
1640 images is reduced by the size of the shared memory.
1641
1642 The shared memory is used to store the CPUs' entrypoint mailbox. On Juno,
1643 this is also used for the MHU payload when passing messages to and from the
1644 SCP.
1645
Soby Mathew492e2452018-06-06 16:03:10 +01001646- Another 4 KB page is reserved for passing memory layout between BL1 and BL2
1647 and also the dynamic firmware configurations.
1648
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001649- On FVP, BL1 is originally sitting in the Trusted ROM at address ``0x0``. On
1650 Juno, BL1 resides in flash memory at address ``0x0BEC0000``. BL1 read-write
1651 data are relocated to the top of Trusted SRAM at runtime.
1652
Soby Mathew492e2452018-06-06 16:03:10 +01001653- BL2 is loaded below BL1 RW
1654
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001655- EL3 Runtime Software, BL31 for AArch64 and BL32 for AArch32 (e.g. SP\_MIN),
1656 is loaded at the top of the Trusted SRAM, such that its NOBITS sections will
Soby Mathew492e2452018-06-06 16:03:10 +01001657 overwrite BL1 R/W data and BL2. This implies that BL1 global variables
1658 remain valid only until execution reaches the EL3 Runtime Software entry
1659 point during a cold boot.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001660
1661- On Juno, SCP\_BL2 is loaded temporarily into the EL3 Runtime Software memory
1662 region and transfered to the SCP before being overwritten by EL3 Runtime
1663 Software.
1664
1665- BL32 (for AArch64) can be loaded in one of the following locations:
1666
1667 - Trusted SRAM
1668 - Trusted DRAM (FVP only)
1669 - Secure region of DRAM (top 16MB of DRAM configured by the TrustZone
1670 controller)
1671
Soby Mathew492e2452018-06-06 16:03:10 +01001672 When BL32 (for AArch64) is loaded into Trusted SRAM, it is loaded below
1673 BL31.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001674
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001675The location of the BL32 image will result in different memory maps. This is
1676illustrated for both FVP and Juno in the following diagrams, using the TSP as
1677an example.
1678
1679Note: Loading the BL32 image in TZC secured DRAM doesn't change the memory
1680layout of the other images in Trusted SRAM.
1681
Soby Mathew492e2452018-06-06 16:03:10 +01001682**FVP with TSP in Trusted SRAM with firmware configs :**
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001683(These diagrams only cover the AArch64 case)
1684
1685::
1686
Soby Mathew492e2452018-06-06 16:03:10 +01001687 DRAM
1688 0xffffffff +----------+
1689 : :
1690 |----------|
1691 |HW_CONFIG |
1692 0x83000000 |----------| (non-secure)
1693 | |
1694 0x80000000 +----------+
1695
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001696 Trusted SRAM
Soby Mathew492e2452018-06-06 16:03:10 +01001697 0x04040000 +----------+ loaded by BL2 +----------------+
1698 | BL1 (rw) | <<<<<<<<<<<<< | |
1699 |----------| <<<<<<<<<<<<< | BL31 NOBITS |
1700 | BL2 | <<<<<<<<<<<<< | |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001701 |----------| <<<<<<<<<<<<< |----------------|
1702 | | <<<<<<<<<<<<< | BL31 PROGBITS |
Soby Mathew492e2452018-06-06 16:03:10 +01001703 | | <<<<<<<<<<<<< |----------------|
1704 | | <<<<<<<<<<<<< | BL32 |
1705 0x04002000 +----------+ +----------------+
1706 |fw_configs|
1707 0x04001000 +----------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001708 | Shared |
1709 0x04000000 +----------+
1710
1711 Trusted ROM
1712 0x04000000 +----------+
1713 | BL1 (ro) |
1714 0x00000000 +----------+
1715
Soby Mathew492e2452018-06-06 16:03:10 +01001716**FVP with TSP in Trusted DRAM with firmware configs (default option):**
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001717
1718::
1719
Soby Mathewb1bf0442018-02-16 14:52:52 +00001720 DRAM
1721 0xffffffff +--------------+
1722 : :
1723 |--------------|
1724 | HW_CONFIG |
1725 0x83000000 |--------------| (non-secure)
1726 | |
1727 0x80000000 +--------------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001728
Soby Mathewb1bf0442018-02-16 14:52:52 +00001729 Trusted DRAM
1730 0x08000000 +--------------+
1731 | BL32 |
1732 0x06000000 +--------------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001733
Soby Mathewb1bf0442018-02-16 14:52:52 +00001734 Trusted SRAM
Soby Mathew492e2452018-06-06 16:03:10 +01001735 0x04040000 +--------------+ loaded by BL2 +----------------+
1736 | BL1 (rw) | <<<<<<<<<<<<< | |
1737 |--------------| <<<<<<<<<<<<< | BL31 NOBITS |
1738 | BL2 | <<<<<<<<<<<<< | |
Soby Mathewb1bf0442018-02-16 14:52:52 +00001739 |--------------| <<<<<<<<<<<<< |----------------|
1740 | | <<<<<<<<<<<<< | BL31 PROGBITS |
Soby Mathew492e2452018-06-06 16:03:10 +01001741 | | +----------------+
1742 +--------------+
1743 | fw_configs |
Soby Mathewb1bf0442018-02-16 14:52:52 +00001744 0x04001000 +--------------+
1745 | Shared |
1746 0x04000000 +--------------+
1747
1748 Trusted ROM
1749 0x04000000 +--------------+
1750 | BL1 (ro) |
1751 0x00000000 +--------------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001752
Soby Mathew492e2452018-06-06 16:03:10 +01001753**FVP with TSP in TZC-Secured DRAM with firmware configs :**
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001754
1755::
1756
1757 DRAM
1758 0xffffffff +----------+
Soby Mathewb1bf0442018-02-16 14:52:52 +00001759 | BL32 | (secure)
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001760 0xff000000 +----------+
1761 | |
Soby Mathew492e2452018-06-06 16:03:10 +01001762 |----------|
1763 |HW_CONFIG |
1764 0x83000000 |----------| (non-secure)
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001765 | |
1766 0x80000000 +----------+
1767
1768 Trusted SRAM
Soby Mathew492e2452018-06-06 16:03:10 +01001769 0x04040000 +----------+ loaded by BL2 +----------------+
1770 | BL1 (rw) | <<<<<<<<<<<<< | |
1771 |----------| <<<<<<<<<<<<< | BL31 NOBITS |
1772 | BL2 | <<<<<<<<<<<<< | |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001773 |----------| <<<<<<<<<<<<< |----------------|
1774 | | <<<<<<<<<<<<< | BL31 PROGBITS |
Soby Mathew492e2452018-06-06 16:03:10 +01001775 | | +----------------+
1776 0x04002000 +----------+
1777 |fw_configs|
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001778 0x04001000 +----------+
1779 | Shared |
1780 0x04000000 +----------+
1781
1782 Trusted ROM
1783 0x04000000 +----------+
1784 | BL1 (ro) |
1785 0x00000000 +----------+
1786
Soby Mathew492e2452018-06-06 16:03:10 +01001787**Juno with BL32 in Trusted SRAM :**
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001788
1789::
1790
1791 Flash0
1792 0x0C000000 +----------+
1793 : :
1794 0x0BED0000 |----------|
1795 | BL1 (ro) |
1796 0x0BEC0000 |----------|
1797 : :
1798 0x08000000 +----------+ BL31 is loaded
1799 after SCP_BL2 has
1800 Trusted SRAM been sent to SCP
Soby Mathew492e2452018-06-06 16:03:10 +01001801 0x04040000 +----------+ loaded by BL2 +----------------+
1802 | BL1 (rw) | <<<<<<<<<<<<< | |
1803 |----------| <<<<<<<<<<<<< | BL31 NOBITS |
1804 | BL2 | <<<<<<<<<<<<< | |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001805 |----------| <<<<<<<<<<<<< |----------------|
1806 | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001807 |----------| <<<<<<<<<<<<< |----------------|
Soby Mathew492e2452018-06-06 16:03:10 +01001808 | | <<<<<<<<<<<<< | BL32 |
1809 | | +----------------+
1810 | |
1811 0x04001000 +----------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001812 | MHU |
1813 0x04000000 +----------+
1814
Soby Mathew492e2452018-06-06 16:03:10 +01001815**Juno with BL32 in TZC-secured DRAM :**
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001816
1817::
1818
1819 DRAM
1820 0xFFE00000 +----------+
Soby Mathewb1bf0442018-02-16 14:52:52 +00001821 | BL32 | (secure)
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001822 0xFF000000 |----------|
1823 | |
1824 : : (non-secure)
1825 | |
1826 0x80000000 +----------+
1827
1828 Flash0
1829 0x0C000000 +----------+
1830 : :
1831 0x0BED0000 |----------|
1832 | BL1 (ro) |
1833 0x0BEC0000 |----------|
1834 : :
1835 0x08000000 +----------+ BL31 is loaded
1836 after SCP_BL2 has
1837 Trusted SRAM been sent to SCP
Soby Mathew492e2452018-06-06 16:03:10 +01001838 0x04040000 +----------+ loaded by BL2 +----------------+
1839 | BL1 (rw) | <<<<<<<<<<<<< | |
1840 |----------| <<<<<<<<<<<<< | BL31 NOBITS |
1841 | BL2 | <<<<<<<<<<<<< | |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001842 |----------| <<<<<<<<<<<<< |----------------|
1843 | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS |
Soby Mathew492e2452018-06-06 16:03:10 +01001844 |----------| +----------------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001845 0x04001000 +----------+
1846 | MHU |
1847 0x04000000 +----------+
1848
1849Firmware Image Package (FIP)
1850----------------------------
1851
1852Using a Firmware Image Package (FIP) allows for packing bootloader images (and
Dan Handley610e7e12018-03-01 18:44:00 +00001853potentially other payloads) into a single archive that can be loaded by TF-A
1854from non-volatile platform storage. A driver to load images from a FIP has
1855been added to the storage layer and allows a package to be read from supported
1856platform storage. A tool to create Firmware Image Packages is also provided
1857and described below.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001858
1859Firmware Image Package layout
1860~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1861
1862The FIP layout consists of a table of contents (ToC) followed by payload data.
1863The ToC itself has a header followed by one or more table entries. The ToC is
Jett Zhou75566102017-11-24 16:03:58 +08001864terminated by an end marker entry, and since the size of the ToC is 0 bytes,
1865the offset equals the total size of the FIP file. All ToC entries describe some
1866payload data that has been appended to the end of the binary package. With the
1867information provided in the ToC entry the corresponding payload data can be
1868retrieved.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001869
1870::
1871
1872 ------------------
1873 | ToC Header |
1874 |----------------|
1875 | ToC Entry 0 |
1876 |----------------|
1877 | ToC Entry 1 |
1878 |----------------|
1879 | ToC End Marker |
1880 |----------------|
1881 | |
1882 | Data 0 |
1883 | |
1884 |----------------|
1885 | |
1886 | Data 1 |
1887 | |
1888 ------------------
1889
1890The ToC header and entry formats are described in the header file
1891``include/tools_share/firmware_image_package.h``. This file is used by both the
Dan Handley610e7e12018-03-01 18:44:00 +00001892tool and TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001893
1894The ToC header has the following fields:
1895
1896::
1897
1898 `name`: The name of the ToC. This is currently used to validate the header.
1899 `serial_number`: A non-zero number provided by the creation tool
1900 `flags`: Flags associated with this data.
1901 Bits 0-31: Reserved
1902 Bits 32-47: Platform defined
1903 Bits 48-63: Reserved
1904
1905A ToC entry has the following fields:
1906
1907::
1908
1909 `uuid`: All files are referred to by a pre-defined Universally Unique
1910 IDentifier [UUID] . The UUIDs are defined in
1911 `include/tools_share/firmware_image_package.h`. The platform translates
1912 the requested image name into the corresponding UUID when accessing the
1913 package.
1914 `offset_address`: The offset address at which the corresponding payload data
1915 can be found. The offset is calculated from the ToC base address.
1916 `size`: The size of the corresponding payload data in bytes.
Etienne Carriere7421bf12017-08-23 15:43:33 +02001917 `flags`: Flags associated with this entry. None are yet defined.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001918
1919Firmware Image Package creation tool
1920~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1921
Dan Handley610e7e12018-03-01 18:44:00 +00001922The FIP creation tool can be used to pack specified images into a binary
1923package that can be loaded by TF-A from platform storage. The tool currently
1924only supports packing bootloader images. Additional image definitions can be
1925added to the tool as required.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001926
1927The tool can be found in ``tools/fiptool``.
1928
1929Loading from a Firmware Image Package (FIP)
1930~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1931
1932The Firmware Image Package (FIP) driver can load images from a binary package on
Dan Handley610e7e12018-03-01 18:44:00 +00001933non-volatile platform storage. For the Arm development platforms, this is
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001934currently NOR FLASH.
1935
1936Bootloader images are loaded according to the platform policy as specified by
Dan Handley610e7e12018-03-01 18:44:00 +00001937the function ``plat_get_image_source()``. For the Arm development platforms, this
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001938means the platform will attempt to load images from a Firmware Image Package
1939located at the start of NOR FLASH0.
1940
Dan Handley610e7e12018-03-01 18:44:00 +00001941The Arm development platforms' policy is to only allow loading of a known set of
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001942images. The platform policy can be modified to allow additional images.
1943
Dan Handley610e7e12018-03-01 18:44:00 +00001944Use of coherent memory in TF-A
1945------------------------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001946
1947There might be loss of coherency when physical memory with mismatched
1948shareability, cacheability and memory attributes is accessed by multiple CPUs
Dan Handley610e7e12018-03-01 18:44:00 +00001949(refer to section B2.9 of `Arm ARM`_ for more details). This possibility occurs
1950in TF-A during power up/down sequences when coherency, MMU and caches are
1951turned on/off incrementally.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001952
Dan Handley610e7e12018-03-01 18:44:00 +00001953TF-A defines coherent memory as a region of memory with Device nGnRE attributes
1954in the translation tables. The translation granule size in TF-A is 4KB. This
1955is the smallest possible size of the coherent memory region.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001956
1957By default, all data structures which are susceptible to accesses with
1958mismatched attributes from various CPUs are allocated in a coherent memory
1959region (refer to section 2.1 of `Porting Guide`_). The coherent memory region
1960accesses are Outer Shareable, non-cacheable and they can be accessed
1961with the Device nGnRE attributes when the MMU is turned on. Hence, at the
Dan Handley610e7e12018-03-01 18:44:00 +00001962expense of at least an extra page of memory, TF-A is able to work around
1963coherency issues due to mismatched memory attributes.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001964
1965The alternative to the above approach is to allocate the susceptible data
1966structures in Normal WriteBack WriteAllocate Inner shareable memory. This
1967approach requires the data structures to be designed so that it is possible to
1968work around the issue of mismatched memory attributes by performing software
1969cache maintenance on them.
1970
Dan Handley610e7e12018-03-01 18:44:00 +00001971Disabling the use of coherent memory in TF-A
1972~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001973
1974It might be desirable to avoid the cost of allocating coherent memory on
Dan Handley610e7e12018-03-01 18:44:00 +00001975platforms which are memory constrained. TF-A enables inclusion of coherent
1976memory in firmware images through the build flag ``USE_COHERENT_MEM``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001977This flag is enabled by default. It can be disabled to choose the second
1978approach described above.
1979
1980The below sections analyze the data structures allocated in the coherent memory
1981region and the changes required to allocate them in normal memory.
1982
1983Coherent memory usage in PSCI implementation
1984~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1985
1986The ``psci_non_cpu_pd_nodes`` data structure stores the platform's power domain
1987tree information for state management of power domains. By default, this data
Dan Handley610e7e12018-03-01 18:44:00 +00001988structure is allocated in the coherent memory region in TF-A because it can be
1989accessed by multple CPUs, either with caches enabled or disabled.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001990
1991.. code:: c
1992
1993 typedef struct non_cpu_pwr_domain_node {
1994 /*
1995 * Index of the first CPU power domain node level 0 which has this node
1996 * as its parent.
1997 */
1998 unsigned int cpu_start_idx;
1999
2000 /*
2001 * Number of CPU power domains which are siblings of the domain indexed
2002 * by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx
2003 * -> cpu_start_idx + ncpus' have this node as their parent.
2004 */
2005 unsigned int ncpus;
2006
2007 /*
2008 * Index of the parent power domain node.
2009 * TODO: Figure out whether to whether using pointer is more efficient.
2010 */
2011 unsigned int parent_node;
2012
2013 plat_local_state_t local_state;
2014
2015 unsigned char level;
2016
2017 /* For indexing the psci_lock array*/
2018 unsigned char lock_index;
2019 } non_cpu_pd_node_t;
2020
2021In order to move this data structure to normal memory, the use of each of its
2022fields must be analyzed. Fields like ``cpu_start_idx``, ``ncpus``, ``parent_node``
2023``level`` and ``lock_index`` are only written once during cold boot. Hence removing
2024them from coherent memory involves only doing a clean and invalidate of the
2025cache lines after these fields are written.
2026
2027The field ``local_state`` can be concurrently accessed by multiple CPUs in
2028different cache states. A Lamport's Bakery lock ``psci_locks`` is used to ensure
2029mutual exlusion to this field and a clean and invalidate is needed after it
2030is written.
2031
2032Bakery lock data
2033~~~~~~~~~~~~~~~~
2034
2035The bakery lock data structure ``bakery_lock_t`` is allocated in coherent memory
2036and is accessed by multiple CPUs with mismatched attributes. ``bakery_lock_t`` is
2037defined as follows:
2038
2039.. code:: c
2040
2041 typedef struct bakery_lock {
2042 /*
2043 * The lock_data is a bit-field of 2 members:
2044 * Bit[0] : choosing. This field is set when the CPU is
2045 * choosing its bakery number.
2046 * Bits[1 - 15] : number. This is the bakery number allocated.
2047 */
2048 volatile uint16_t lock_data[BAKERY_LOCK_MAX_CPUS];
2049 } bakery_lock_t;
2050
2051It is a characteristic of Lamport's Bakery algorithm that the volatile per-CPU
2052fields can be read by all CPUs but only written to by the owning CPU.
2053
2054Depending upon the data cache line size, the per-CPU fields of the
2055``bakery_lock_t`` structure for multiple CPUs may exist on a single cache line.
2056These per-CPU fields can be read and written during lock contention by multiple
2057CPUs with mismatched memory attributes. Since these fields are a part of the
2058lock implementation, they do not have access to any other locking primitive to
2059safeguard against the resulting coherency issues. As a result, simple software
2060cache maintenance is not enough to allocate them in coherent memory. Consider
2061the following example.
2062
2063CPU0 updates its per-CPU field with data cache enabled. This write updates a
2064local cache line which contains a copy of the fields for other CPUs as well. Now
2065CPU1 updates its per-CPU field of the ``bakery_lock_t`` structure with data cache
2066disabled. CPU1 then issues a DCIVAC operation to invalidate any stale copies of
2067its field in any other cache line in the system. This operation will invalidate
2068the update made by CPU0 as well.
2069
2070To use bakery locks when ``USE_COHERENT_MEM`` is disabled, the lock data structure
2071has been redesigned. The changes utilise the characteristic of Lamport's Bakery
2072algorithm mentioned earlier. The bakery\_lock structure only allocates the memory
2073for a single CPU. The macro ``DEFINE_BAKERY_LOCK`` allocates all the bakery locks
2074needed for a CPU into a section ``bakery_lock``. The linker allocates the memory
2075for other cores by using the total size allocated for the bakery\_lock section
2076and multiplying it with (PLATFORM\_CORE\_COUNT - 1). This enables software to
2077perform software cache maintenance on the lock data structure without running
2078into coherency issues associated with mismatched attributes.
2079
2080The bakery lock data structure ``bakery_info_t`` is defined for use when
2081``USE_COHERENT_MEM`` is disabled as follows:
2082
2083.. code:: c
2084
2085 typedef struct bakery_info {
2086 /*
2087 * The lock_data is a bit-field of 2 members:
2088 * Bit[0] : choosing. This field is set when the CPU is
2089 * choosing its bakery number.
2090 * Bits[1 - 15] : number. This is the bakery number allocated.
2091 */
2092 volatile uint16_t lock_data;
2093 } bakery_info_t;
2094
2095The ``bakery_info_t`` represents a single per-CPU field of one lock and
2096the combination of corresponding ``bakery_info_t`` structures for all CPUs in the
2097system represents the complete bakery lock. The view in memory for a system
2098with n bakery locks are:
2099
2100::
2101
2102 bakery_lock section start
2103 |----------------|
2104 | `bakery_info_t`| <-- Lock_0 per-CPU field
2105 | Lock_0 | for CPU0
2106 |----------------|
2107 | `bakery_info_t`| <-- Lock_1 per-CPU field
2108 | Lock_1 | for CPU0
2109 |----------------|
2110 | .... |
2111 |----------------|
2112 | `bakery_info_t`| <-- Lock_N per-CPU field
2113 | Lock_N | for CPU0
2114 ------------------
2115 | XXXXX |
2116 | Padding to |
2117 | next Cache WB | <--- Calculate PERCPU_BAKERY_LOCK_SIZE, allocate
2118 | Granule | continuous memory for remaining CPUs.
2119 ------------------
2120 | `bakery_info_t`| <-- Lock_0 per-CPU field
2121 | Lock_0 | for CPU1
2122 |----------------|
2123 | `bakery_info_t`| <-- Lock_1 per-CPU field
2124 | Lock_1 | for CPU1
2125 |----------------|
2126 | .... |
2127 |----------------|
2128 | `bakery_info_t`| <-- Lock_N per-CPU field
2129 | Lock_N | for CPU1
2130 ------------------
2131 | XXXXX |
2132 | Padding to |
2133 | next Cache WB |
2134 | Granule |
2135 ------------------
2136
2137Consider a system of 2 CPUs with 'N' bakery locks as shown above. For an
2138operation on Lock\_N, the corresponding ``bakery_info_t`` in both CPU0 and CPU1
2139``bakery_lock`` section need to be fetched and appropriate cache operations need
2140to be performed for each access.
2141
Dan Handley610e7e12018-03-01 18:44:00 +00002142On Arm Platforms, bakery locks are used in psci (``psci_locks``) and power controller
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002143driver (``arm_lock``).
2144
2145Non Functional Impact of removing coherent memory
2146~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2147
2148Removal of the coherent memory region leads to the additional software overhead
2149of performing cache maintenance for the affected data structures. However, since
2150the memory where the data structures are allocated is cacheable, the overhead is
2151mostly mitigated by an increase in performance.
2152
2153There is however a performance impact for bakery locks, due to:
2154
2155- Additional cache maintenance operations, and
2156- Multiple cache line reads for each lock operation, since the bakery locks
2157 for each CPU are distributed across different cache lines.
2158
2159The implementation has been optimized to minimize this additional overhead.
2160Measurements indicate that when bakery locks are allocated in Normal memory, the
2161minimum latency of acquiring a lock is on an average 3-4 micro seconds whereas
2162in Device memory the same is 2 micro seconds. The measurements were done on the
Dan Handley610e7e12018-03-01 18:44:00 +00002163Juno Arm development platform.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002164
2165As mentioned earlier, almost a page of memory can be saved by disabling
2166``USE_COHERENT_MEM``. Each platform needs to consider these trade-offs to decide
2167whether coherent memory should be used. If a platform disables
2168``USE_COHERENT_MEM`` and needs to use bakery locks in the porting layer, it can
2169optionally define macro ``PLAT_PERCPU_BAKERY_LOCK_SIZE`` (see the
2170`Porting Guide`_). Refer to the reference platform code for examples.
2171
2172Isolating code and read-only data on separate memory pages
2173----------------------------------------------------------
2174
Dan Handley610e7e12018-03-01 18:44:00 +00002175In the Armv8-A VMSA, translation table entries include fields that define the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002176properties of the target memory region, such as its access permissions. The
2177smallest unit of memory that can be addressed by a translation table entry is
2178a memory page. Therefore, if software needs to set different permissions on two
2179memory regions then it needs to map them using different memory pages.
2180
2181The default memory layout for each BL image is as follows:
2182
2183::
2184
2185 | ... |
2186 +-------------------+
2187 | Read-write data |
2188 +-------------------+ Page boundary
2189 | <Padding> |
2190 +-------------------+
2191 | Exception vectors |
2192 +-------------------+ 2 KB boundary
2193 | <Padding> |
2194 +-------------------+
2195 | Read-only data |
2196 +-------------------+
2197 | Code |
2198 +-------------------+ BLx_BASE
2199
2200Note: The 2KB alignment for the exception vectors is an architectural
2201requirement.
2202
2203The read-write data start on a new memory page so that they can be mapped with
2204read-write permissions, whereas the code and read-only data below are configured
2205as read-only.
2206
2207However, the read-only data are not aligned on a page boundary. They are
2208contiguous to the code. Therefore, the end of the code section and the beginning
2209of the read-only data one might share a memory page. This forces both to be
2210mapped with the same memory attributes. As the code needs to be executable, this
2211means that the read-only data stored on the same memory page as the code are
2212executable as well. This could potentially be exploited as part of a security
2213attack.
2214
2215TF provides the build flag ``SEPARATE_CODE_AND_RODATA`` to isolate the code and
2216read-only data on separate memory pages. This in turn allows independent control
2217of the access permissions for the code and read-only data. In this case,
2218platform code gets a finer-grained view of the image layout and can
2219appropriately map the code region as executable and the read-only data as
2220execute-never.
2221
2222This has an impact on memory footprint, as padding bytes need to be introduced
2223between the code and read-only data to ensure the segragation of the two. To
2224limit the memory cost, this flag also changes the memory layout such that the
2225code and exception vectors are now contiguous, like so:
2226
2227::
2228
2229 | ... |
2230 +-------------------+
2231 | Read-write data |
2232 +-------------------+ Page boundary
2233 | <Padding> |
2234 +-------------------+
2235 | Read-only data |
2236 +-------------------+ Page boundary
2237 | <Padding> |
2238 +-------------------+
2239 | Exception vectors |
2240 +-------------------+ 2 KB boundary
2241 | <Padding> |
2242 +-------------------+
2243 | Code |
2244 +-------------------+ BLx_BASE
2245
2246With this more condensed memory layout, the separation of read-only data will
2247add zero or one page to the memory footprint of each BL image. Each platform
2248should consider the trade-off between memory footprint and security.
2249
Dan Handley610e7e12018-03-01 18:44:00 +00002250This build flag is disabled by default, minimising memory footprint. On Arm
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002251platforms, it is enabled.
2252
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002253Publish and Subscribe Framework
2254-------------------------------
2255
2256The Publish and Subscribe Framework allows EL3 components to define and publish
2257events, to which other EL3 components can subscribe.
2258
2259The following macros are provided by the framework:
2260
2261- ``REGISTER_PUBSUB_EVENT(event)``: Defines an event, and takes one argument,
2262 the event name, which must be a valid C identifier. All calls to
2263 ``REGISTER_PUBSUB_EVENT`` macro must be placed in the file
2264 ``pubsub_events.h``.
2265
2266- ``PUBLISH_EVENT_ARG(event, arg)``: Publishes a defined event, by iterating
2267 subscribed handlers and calling them in turn. The handlers will be passed the
2268 parameter ``arg``. The expected use-case is to broadcast an event.
2269
2270- ``PUBLISH_EVENT(event)``: Like ``PUBLISH_EVENT_ARG``, except that the value
2271 ``NULL`` is passed to subscribed handlers.
2272
2273- ``SUBSCRIBE_TO_EVENT(event, handler)``: Registers the ``handler`` to
2274 subscribe to ``event``. The handler will be executed whenever the ``event``
2275 is published.
2276
2277- ``for_each_subscriber(event, subscriber)``: Iterates through all handlers
2278 subscribed for ``event``. ``subscriber`` must be a local variable of type
2279 ``pubsub_cb_t *``, and will point to each subscribed handler in turn during
2280 iteration. This macro can be used for those patterns that none of the
2281 ``PUBLISH_EVENT_*()`` macros cover.
2282
2283Publishing an event that wasn't defined using ``REGISTER_PUBSUB_EVENT`` will
2284result in build error. Subscribing to an undefined event however won't.
2285
2286Subscribed handlers must be of type ``pubsub_cb_t``, with following function
2287signature:
2288
2289::
2290
2291 typedef void* (*pubsub_cb_t)(const void *arg);
2292
2293There may be arbitrary number of handlers registered to the same event. The
2294order in which subscribed handlers are notified when that event is published is
2295not defined. Subscribed handlers may be executed in any order; handlers should
2296not assume any relative ordering amongst them.
2297
2298Publishing an event on a PE will result in subscribed handlers executing on that
2299PE only; it won't cause handlers to execute on a different PE.
2300
2301Note that publishing an event on a PE blocks until all the subscribed handlers
2302finish executing on the PE.
2303
Dan Handley610e7e12018-03-01 18:44:00 +00002304TF-A generic code publishes and subscribes to some events within. Platform
2305ports are discouraged from subscribing to them. These events may be withdrawn,
2306renamed, or have their semantics altered in the future. Platforms may however
2307register, publish, and subscribe to platform-specific events.
Dimitris Papastamosa7921b92017-10-13 15:27:58 +01002308
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002309Publish and Subscribe Example
2310~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2311
2312A publisher that wants to publish event ``foo`` would:
2313
2314- Define the event ``foo`` in the ``pubsub_events.h``.
2315
2316 ::
2317
2318 REGISTER_PUBSUB_EVENT(foo);
2319
2320- Depending on the nature of event, use one of ``PUBLISH_EVENT_*()`` macros to
2321 publish the event at the appropriate path and time of execution.
2322
2323A subscriber that wants to subscribe to event ``foo`` published above would
2324implement:
2325
2326::
2327
2328 void *foo_handler(const void *arg)
2329 {
2330 void *result;
2331
2332 /* Do handling ... */
2333
2334 return result;
2335 }
2336
2337 SUBSCRIBE_TO_EVENT(foo, foo_handler);
2338
Daniel Boulby468f0d72018-09-18 11:45:51 +01002339
2340Reclaiming the BL31 initialization code
2341~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2342
2343A significant amount of the code used for the initialization of BL31 is never
2344needed again after boot time. In order to reduce the runtime memory
2345footprint, the memory used for this code can be reclaimed after initialization
2346has finished and be used for runtime data.
2347
2348The build option ``RECLAIM_INIT_CODE`` can be set to mark this boot time code
2349with a ``.text.init.*`` attribute which can be filtered and placed suitably
2350within the BL image for later reclaimation by the platform. The platform can
2351specify the fiter and the memory region for this init section in BL31 via the
2352plat.ld.S linker script. For example, on the FVP, this section is placed
2353overlapping the secondary CPU stacks so that after the cold boot is done, this
2354memory can be reclaimed for the stacks. The init memory section is initially
2355mapped with ``RO``, ``EXECUTE`` attributes. After BL31 initilization has
2356completed, the FVP changes the attributes of this section to ``RW``,
2357``EXECUTE_NEVER`` allowing it to be used for runtime data. The memory attributes
2358are changed within the ``bl31_plat_runtime_setup`` platform hook. The init
2359section section can be reclaimed for any data which is accessed after cold
2360boot initialization and it is upto the platform to make the decision.
2361
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002362Performance Measurement Framework
2363---------------------------------
2364
2365The Performance Measurement Framework (PMF) facilitates collection of
Dan Handley610e7e12018-03-01 18:44:00 +00002366timestamps by registered services and provides interfaces to retrieve them
2367from within TF-A. A platform can choose to expose appropriate SMCs to
2368retrieve these collected timestamps.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002369
2370By default, the global physical counter is used for the timestamp
2371value and is read via ``CNTPCT_EL0``. The framework allows to retrieve
2372timestamps captured by other CPUs.
2373
2374Timestamp identifier format
2375~~~~~~~~~~~~~~~~~~~~~~~~~~~
2376
2377A PMF timestamp is uniquely identified across the system via the
2378timestamp ID or ``tid``. The ``tid`` is composed as follows:
2379
2380::
2381
2382 Bits 0-7: The local timestamp identifier.
2383 Bits 8-9: Reserved.
2384 Bits 10-15: The service identifier.
2385 Bits 16-31: Reserved.
2386
2387#. The service identifier. Each PMF service is identified by a
2388 service name and a service identifier. Both the service name and
2389 identifier are unique within the system as a whole.
2390
2391#. The local timestamp identifier. This identifier is unique within a given
2392 service.
2393
2394Registering a PMF service
2395~~~~~~~~~~~~~~~~~~~~~~~~~
2396
2397To register a PMF service, the ``PMF_REGISTER_SERVICE()`` macro from ``pmf.h``
2398is used. The arguments required are the service name, the service ID,
2399the total number of local timestamps to be captured and a set of flags.
2400
2401The ``flags`` field can be specified as a bitwise-OR of the following values:
2402
2403::
2404
2405 PMF_STORE_ENABLE: The timestamp is stored in memory for later retrieval.
2406 PMF_DUMP_ENABLE: The timestamp is dumped on the serial console.
2407
2408The ``PMF_REGISTER_SERVICE()`` reserves memory to store captured
2409timestamps in a PMF specific linker section at build time.
2410Additionally, it defines necessary functions to capture and
2411retrieve a particular timestamp for the given service at runtime.
2412
Dan Handley610e7e12018-03-01 18:44:00 +00002413The macro ``PMF_REGISTER_SERVICE()`` only enables capturing PMF timestamps
2414from within TF-A. In order to retrieve timestamps from outside of TF-A, the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002415``PMF_REGISTER_SERVICE_SMC()`` macro must be used instead. This macro
2416accepts the same set of arguments as the ``PMF_REGISTER_SERVICE()``
2417macro but additionally supports retrieving timestamps using SMCs.
2418
2419Capturing a timestamp
2420~~~~~~~~~~~~~~~~~~~~~
2421
2422PMF timestamps are stored in a per-service timestamp region. On a
2423system with multiple CPUs, each timestamp is captured and stored
2424in a per-CPU cache line aligned memory region.
2425
2426Having registered the service, the ``PMF_CAPTURE_TIMESTAMP()`` macro can be
2427used to capture a timestamp at the location where it is used. The macro
2428takes the service name, a local timestamp identifier and a flag as arguments.
2429
2430The ``flags`` field argument can be zero, or ``PMF_CACHE_MAINT`` which
2431instructs PMF to do cache maintenance following the capture. Cache
2432maintenance is required if any of the service's timestamps are captured
2433with data cache disabled.
2434
2435To capture a timestamp in assembly code, the caller should use
2436``pmf_calc_timestamp_addr`` macro (defined in ``pmf_asm_macros.S``) to
2437calculate the address of where the timestamp would be stored. The
2438caller should then read ``CNTPCT_EL0`` register to obtain the timestamp
2439and store it at the determined address for later retrieval.
2440
2441Retrieving a timestamp
2442~~~~~~~~~~~~~~~~~~~~~~
2443
Dan Handley610e7e12018-03-01 18:44:00 +00002444From within TF-A, timestamps for individual CPUs can be retrieved using either
2445``PMF_GET_TIMESTAMP_BY_MPIDR()`` or ``PMF_GET_TIMESTAMP_BY_INDEX()`` macros.
2446These macros accept the CPU's MPIDR value, or its ordinal position
2447respectively.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002448
Dan Handley610e7e12018-03-01 18:44:00 +00002449From outside TF-A, timestamps for individual CPUs can be retrieved by calling
2450into ``pmf_smc_handler()``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002451
2452.. code:: c
2453
2454 Interface : pmf_smc_handler()
2455 Argument : unsigned int smc_fid, u_register_t x1,
2456 u_register_t x2, u_register_t x3,
2457 u_register_t x4, void *cookie,
2458 void *handle, u_register_t flags
2459 Return : uintptr_t
2460
2461 smc_fid: Holds the SMC identifier which is either `PMF_SMC_GET_TIMESTAMP_32`
2462 when the caller of the SMC is running in AArch32 mode
2463 or `PMF_SMC_GET_TIMESTAMP_64` when the caller is running in AArch64 mode.
2464 x1: Timestamp identifier.
2465 x2: The `mpidr` of the CPU for which the timestamp has to be retrieved.
2466 This can be the `mpidr` of a different core to the one initiating
2467 the SMC. In that case, service specific cache maintenance may be
2468 required to ensure the updated copy of the timestamp is returned.
2469 x3: A flags value that is either 0 or `PMF_CACHE_MAINT`. If
2470 `PMF_CACHE_MAINT` is passed, then the PMF code will perform a
2471 cache invalidate before reading the timestamp. This ensures
2472 an updated copy is returned.
2473
2474The remaining arguments, ``x4``, ``cookie``, ``handle`` and ``flags`` are unused
2475in this implementation.
2476
2477PMF code structure
2478~~~~~~~~~~~~~~~~~~
2479
2480#. ``pmf_main.c`` consists of core functions that implement service registration,
2481 initialization, storing, dumping and retrieving timestamps.
2482
2483#. ``pmf_smc.c`` contains the SMC handling for registered PMF services.
2484
2485#. ``pmf.h`` contains the public interface to Performance Measurement Framework.
2486
2487#. ``pmf_asm_macros.S`` consists of macros to facilitate capturing timestamps in
2488 assembly code.
2489
2490#. ``pmf_helpers.h`` is an internal header used by ``pmf.h``.
2491
Dan Handley610e7e12018-03-01 18:44:00 +00002492Armv8-A Architecture Extensions
2493-------------------------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002494
Dan Handley610e7e12018-03-01 18:44:00 +00002495TF-A makes use of Armv8-A Architecture Extensions where applicable. This
2496section lists the usage of Architecture Extensions, and build flags
2497controlling them.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002498
2499In general, and unless individually mentioned, the build options
2500``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR`` selects the Architecture Extension to
Dan Handley610e7e12018-03-01 18:44:00 +00002501target when building TF-A. Subsequent Arm Architecture Extensions are backward
2502compatible with previous versions.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002503
2504The build system only requires that ``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR`` have a
2505valid numeric value. These build options only control whether or not
Dan Handley610e7e12018-03-01 18:44:00 +00002506Architecture Extension-specific code is included in the build. Otherwise, TF-A
2507targets the base Armv8.0-A architecture; i.e. as if ``ARM_ARCH_MAJOR`` == 8
2508and ``ARM_ARCH_MINOR`` == 0, which are also their respective default values.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002509
2510See also the *Summary of build options* in `User Guide`_.
2511
2512For details on the Architecture Extension and available features, please refer
2513to the respective Architecture Extension Supplement.
2514
Dan Handley610e7e12018-03-01 18:44:00 +00002515Armv8.1-A
2516~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002517
2518This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` >= 8, or when
2519``ARM_ARCH_MAJOR`` == 8 and ``ARM_ARCH_MINOR`` >= 1.
2520
2521- The Compare and Swap instruction is used to implement spinlocks. Otherwise,
2522 the load-/store-exclusive instruction pair is used.
2523
Dan Handley610e7e12018-03-01 18:44:00 +00002524Armv8.2-A
2525~~~~~~~~~
Isla Mitchellc4a1a072017-08-07 11:20:13 +01002526
2527This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` == 8 and
2528``ARM_ARCH_MINOR`` >= 2.
2529
2530- The Common not Private (CnP) bit is enabled to indicate that multiple
Sandrine Bailleuxfee6e262018-01-29 14:48:15 +01002531 Processing Elements in the same Inner Shareable domain use the same
2532 translation table entries for a given stage of translation for a particular
2533 translation regime.
Isla Mitchellc4a1a072017-08-07 11:20:13 +01002534
Dan Handley610e7e12018-03-01 18:44:00 +00002535Armv7-A
2536~~~~~~~
Etienne Carriere1374fcb2017-11-08 13:48:40 +01002537
2538This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` == 7.
2539
Dan Handley610e7e12018-03-01 18:44:00 +00002540There are several Armv7-A extensions available. Obviously the TrustZone
2541extension is mandatory to support the TF-A bootloader and runtime services.
Etienne Carriere1374fcb2017-11-08 13:48:40 +01002542
Dan Handley610e7e12018-03-01 18:44:00 +00002543Platform implementing an Armv7-A system can to define from its target
Etienne Carriere1374fcb2017-11-08 13:48:40 +01002544Cortex-A architecture through ``ARM_CORTEX_A<X> = yes`` in their
2545``plaform.mk`` script. For example ``ARM_CORTEX_A15=yes`` for a
2546Cortex-A15 target.
2547
2548Platform can also set ``ARM_WITH_NEON=yes`` to enable neon support.
2549Note that using neon at runtime has constraints on non secure wolrd context.
Dan Handley610e7e12018-03-01 18:44:00 +00002550TF-A does not yet provide VFP context management.
Etienne Carriere1374fcb2017-11-08 13:48:40 +01002551
2552Directive ``ARM_CORTEX_A<x>`` and ``ARM_WITH_NEON`` are used to set
2553the toolchain target architecture directive.
2554
2555Platform may choose to not define straight the toolchain target architecture
2556directive by defining ``MARCH32_DIRECTIVE``.
2557I.e:
2558
2559::
2560
2561 MARCH32_DIRECTIVE := -mach=armv7-a
2562
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002563Code Structure
2564--------------
2565
Dan Handley610e7e12018-03-01 18:44:00 +00002566TF-A code is logically divided between the three boot loader stages mentioned
2567in the previous sections. The code is also divided into the following
2568categories (present as directories in the source code):
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002569
2570- **Platform specific.** Choice of architecture specific code depends upon
2571 the platform.
2572- **Common code.** This is platform and architecture agnostic code.
2573- **Library code.** This code comprises of functionality commonly used by all
2574 other code. The PSCI implementation and other EL3 runtime frameworks reside
2575 as Library components.
2576- **Stage specific.** Code specific to a boot stage.
2577- **Drivers.**
2578- **Services.** EL3 runtime services (eg: SPD). Specific SPD services
2579 reside in the ``services/spd`` directory (e.g. ``services/spd/tspd``).
2580
2581Each boot loader stage uses code from one or more of the above mentioned
2582categories. Based upon the above, the code layout looks like this:
2583
2584::
2585
2586 Directory Used by BL1? Used by BL2? Used by BL31?
2587 bl1 Yes No No
2588 bl2 No Yes No
2589 bl31 No No Yes
2590 plat Yes Yes Yes
2591 drivers Yes No Yes
2592 common Yes Yes Yes
2593 lib Yes Yes Yes
2594 services No No Yes
2595
2596The build system provides a non configurable build option IMAGE\_BLx for each
2597boot loader stage (where x = BL stage). e.g. for BL1 , IMAGE\_BL1 will be
Dan Handley610e7e12018-03-01 18:44:00 +00002598defined by the build system. This enables TF-A to compile certain code only
2599for specific boot loader stages
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002600
2601All assembler files have the ``.S`` extension. The linker source files for each
2602boot stage have the extension ``.ld.S``. These are processed by GCC to create the
2603linker scripts which have the extension ``.ld``.
2604
2605FDTs provide a description of the hardware platform and are used by the Linux
2606kernel at boot time. These can be found in the ``fdts`` directory.
2607
2608References
2609----------
2610
Dan Handley610e7e12018-03-01 18:44:00 +00002611.. [#] Trusted Board Boot Requirements CLIENT PDD (Arm DEN0006C-1). Available
2612 under NDA through your Arm account representative.
Douglas Raillard30d7b362017-06-28 16:14:55 +01002613.. [#] `Power State Coordination Interface PDD`_
2614.. [#] `SMC Calling Convention PDD`_
Dan Handley610e7e12018-03-01 18:44:00 +00002615.. [#] `TF-A Interrupt Management Design guide`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002616
2617--------------
2618
Dan Handley610e7e12018-03-01 18:44:00 +00002619*Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.*
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002620
2621.. _Reset Design: ./reset-design.rst
2622.. _Porting Guide: ./porting-guide.rst
2623.. _Firmware Update: ./firmware-update.rst
2624.. _PSCI PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
2625.. _SMC calling convention PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf
2626.. _PSCI Library integration guide: ./psci-lib-integration-guide.rst
2627.. _SMCCC: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf
2628.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
2629.. _Power State Coordination Interface PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
2630.. _here: ./psci-lib-integration-guide.rst
2631.. _cpu-specific-build-macros.rst: ./cpu-specific-build-macros.rst
2632.. _CPUBM: ./cpu-specific-build-macros.rst
Dan Handley610e7e12018-03-01 18:44:00 +00002633.. _Arm ARM: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0487a.e/index.html
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002634.. _User Guide: ./user-guide.rst
2635.. _SMC Calling Convention PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf
Dan Handley610e7e12018-03-01 18:44:00 +00002636.. _TF-A Interrupt Management Design guide: ./interrupt-framework-design.rst
Antonio Nino Diazb5d68092017-05-23 11:49:22 +01002637.. _Xlat_tables design: xlat-tables-lib-v2-design.rst
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002638
2639.. |Image 1| image:: diagrams/rt-svc-descs-layout.png?raw=true