| developer | 4d05507 | 2020-08-25 22:31:14 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2020, MediaTek Inc. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef MTK_PTP3_H |
| 8 | #define MTK_PTP3_H |
| 9 | |
| 10 | #include <lib/mmio.h> |
| 11 | #include <lib/utils_def.h> |
| 12 | |
| 13 | /************************************************ |
| 14 | * BIT Operation and REG r/w |
| 15 | ************************************************/ |
| 16 | #define ptp3_read(addr) mmio_read_32((uintptr_t)addr) |
| 17 | #define ptp3_write(addr, val) mmio_write_32((uintptr_t)addr, val) |
| 18 | |
| 19 | /************************************************ |
| 20 | * CPU info |
| 21 | ************************************************/ |
| 22 | #define NR_PTP3_CFG1_CPU U(8) |
| 23 | #define PTP3_CFG1_CPU_START_ID U(0) |
| 24 | #define PTP3_CFG1_MASK 0x00100000 |
| 25 | |
| 26 | #define NR_PTP3_CFG2_CPU U(4) |
| 27 | #define PTP3_CFG2_CPU_START_ID U(4) |
| 28 | |
| 29 | #define NR_PTP3_CFG3_CPU U(4) |
| 30 | #define PTP3_CFG3_CPU_START_ID U(4) |
| 31 | |
| 32 | /************************************************ |
| 33 | * config enum |
| 34 | ************************************************/ |
| 35 | enum PTP3_CFG { |
| 36 | PTP3_CFG_ADDR, |
| 37 | PTP3_CFG_VALUE, |
| 38 | NR_PTP3_CFG, |
| 39 | }; |
| 40 | |
| 41 | /************************************ |
| 42 | * prototype |
| 43 | ************************************/ |
| 44 | /* init trigger for ptp3 feature */ |
| 45 | extern void ptp3_init(unsigned int core); |
| 46 | extern void ptp3_deinit(unsigned int core); |
| 47 | |
| 48 | #endif /* MTK_PTP3_H */ |