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Andre Przywara452b2b62018-09-28 00:37:19 +01001#
Andre Przywara50bb4172021-01-20 00:09:44 +00002# Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
Andre Przywara452b2b62018-09-28 00:37:19 +01003#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7include lib/xlat_tables_v2/xlat_tables.mk
Andre Przywara92b4c9b2020-08-03 00:25:03 +01008include lib/libfdt/libfdt.mk
9include drivers/arm/gic/v2/gicv2.mk
Andre Przywara452b2b62018-09-28 00:37:19 +010010
11AW_PLAT := plat/allwinner
12
Samuel Holland4a024712019-11-27 13:09:40 -060013PLAT_INCLUDES := -Iinclude/plat/arm/common/aarch64 \
Andre Przywara452b2b62018-09-28 00:37:19 +010014 -I${AW_PLAT}/common/include \
15 -I${AW_PLAT}/${PLAT}/include
16
Julius Werner6b88b652018-11-27 17:50:28 -080017PLAT_BL_COMMON_SOURCES := drivers/ti/uart/${ARCH}/16550_console.S \
Andre Przywara452b2b62018-09-28 00:37:19 +010018 ${XLAT_TABLES_LIB_SRCS} \
19 ${AW_PLAT}/common/plat_helpers.S \
20 ${AW_PLAT}/common/sunxi_common.c
21
Samuel Holland1dad2652019-10-20 21:34:38 -050022BL31_SOURCES += drivers/allwinner/axp/common.c \
Andre Przywara92b4c9b2020-08-03 00:25:03 +010023 ${GICV2_SOURCES} \
Andre Przywara452b2b62018-09-28 00:37:19 +010024 drivers/delay_timer/delay_timer.c \
25 drivers/delay_timer/generic_delay_timer.c \
26 lib/cpus/${ARCH}/cortex_a53.S \
27 plat/common/plat_gicv2.c \
28 plat/common/plat_psci_common.c \
29 ${AW_PLAT}/common/sunxi_bl31_setup.c \
Samuel Holland365966c2022-01-22 23:37:12 -060030 ${AW_PLAT}/${PLAT}/sunxi_idle_states.c \
Andre Przywara452b2b62018-09-28 00:37:19 +010031 ${AW_PLAT}/common/sunxi_pm.c \
32 ${AW_PLAT}/${PLAT}/sunxi_power.c \
33 ${AW_PLAT}/common/sunxi_security.c \
34 ${AW_PLAT}/common/sunxi_topology.c
35
Andre Przywara50bb4172021-01-20 00:09:44 +000036# By default, attempt to use SCPI to the ARISC management processor. If SCPI
37# is not enabled or SCP firmware is not loaded, fall back to a simpler native
38# implementation that does not support CPU or system suspend.
39#
40# If SCP firmware will always be present (or absent), the unused implementation
41# can be compiled out.
42SUNXI_PSCI_USE_NATIVE ?= 1
43SUNXI_PSCI_USE_SCPI ?= 1
44
45$(eval $(call assert_boolean,SUNXI_PSCI_USE_NATIVE))
46$(eval $(call assert_boolean,SUNXI_PSCI_USE_SCPI))
47$(eval $(call add_define,SUNXI_PSCI_USE_NATIVE))
48$(eval $(call add_define,SUNXI_PSCI_USE_SCPI))
49
50ifeq (${SUNXI_PSCI_USE_NATIVE}${SUNXI_PSCI_USE_SCPI},00)
51$(error "At least one of SCPI or native PSCI ops must be enabled")
52endif
53
54ifeq (${SUNXI_PSCI_USE_NATIVE},1)
55BL31_SOURCES += ${AW_PLAT}/common/sunxi_cpu_ops.c \
56 ${AW_PLAT}/common/sunxi_native_pm.c
57endif
58
59ifeq (${SUNXI_PSCI_USE_SCPI},1)
60BL31_SOURCES += drivers/allwinner/sunxi_msgbox.c \
61 drivers/arm/css/scpi/css_scpi.c \
62 ${AW_PLAT}/common/sunxi_scpi_pm.c
63endif
64
Andre Przywara71b5a1d2021-11-01 00:17:37 +000065SUNXI_SETUP_REGULATORS ?= 1
66$(eval $(call assert_boolean,SUNXI_SETUP_REGULATORS))
67$(eval $(call add_define,SUNXI_SETUP_REGULATORS))
68
Andre Przywara9de12222021-12-19 13:39:40 +000069SUNXI_BL31_IN_DRAM ?= 0
70$(eval $(call assert_boolean,SUNXI_BL31_IN_DRAM))
71
72ifeq (${SUNXI_BL31_IN_DRAM},1)
73SUNXI_AMEND_DTB := 1
74$(eval $(call add_define,SUNXI_BL31_IN_DRAM))
75endif
76
77SUNXI_AMEND_DTB ?= 0
78$(eval $(call assert_boolean,SUNXI_AMEND_DTB))
79$(eval $(call add_define,SUNXI_AMEND_DTB))
80
81ifeq (${SUNXI_AMEND_DTB},1)
82BL31_SOURCES += common/fdt_fixup.c \
83 ${AW_PLAT}/common/sunxi_prepare_dtb.c
84endif
85
Andre Przywara452b2b62018-09-28 00:37:19 +010086# The bootloader is guaranteed to only run on CPU 0 by the boot ROM.
87COLD_BOOT_SINGLE_CPU := 1
88
Samuel Hollandc47f00e2019-06-08 16:03:32 -050089# Do not enable SPE (not supported on ARM v8.0).
Andre Przywara30661a92023-02-03 15:30:14 +000090ENABLE_SPE_FOR_NS := 0
Samuel Hollandc47f00e2019-06-08 16:03:32 -050091
92# Do not enable SVE (not supported on ARM v8.0).
93ENABLE_SVE_FOR_NS := 0
94
Andre Przywara452b2b62018-09-28 00:37:19 +010095# Enable workarounds for Cortex-A53 errata. Allwinner uses at least r0p4.
96ERRATA_A53_835769 := 1
97ERRATA_A53_843419 := 1
98ERRATA_A53_855873 := 1
Samuel Holland3784ec92020-12-13 22:22:17 -060099ERRATA_A53_1530924 := 1
Andre Przywara452b2b62018-09-28 00:37:19 +0100100
Samuel Hollandafe21732020-12-13 20:05:11 -0600101# The traditional U-Boot load address is 160MB into DRAM.
102PRELOADED_BL33_BASE ?= 0x4a000000
103
Andre Przywara452b2b62018-09-28 00:37:19 +0100104# The reset vector can be changed for each CPU.
105PROGRAMMABLE_RESET_ADDRESS := 1
106
107# Allow mapping read-only data as execute-never.
108SEPARATE_CODE_AND_RODATA := 1
109
110# BL31 gets loaded alongside BL33 (U-Boot) by U-Boot's SPL
111RESET_TO_BL31 := 1
Andre Przywara647a2e12018-10-11 22:14:30 +0100112
Samuel Hollandc47f00e2019-06-08 16:03:32 -0500113# This platform is single-cluster and does not require coherency setup.
114WARMBOOT_ENABLE_DCACHE_EARLY := 1