blob: 051e46a224b87e0522b504d6c059e237b690ff78 [file] [log] [blame]
Soby Mathew44170c42016-03-22 15:51:08 +00001/*
2 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
32#include <arch_helpers.h>
33#include <assert.h>
34#include <cassert.h>
35#include <platform_def.h>
36#include <xlat_tables.h>
37#include "../xlat_tables_private.h"
38
39#define IS_POWER_OF_TWO(x) (((x) & ((x) - 1)) == 0)
40
41/*
42 * The virtual address space size must be a power of two (as set in TCR.T0SZ).
43 * As we start the initial lookup at level 1, it must also be between 2 GB and
44 * 512 GB (with the virtual address size therefore 31 to 39 bits). See section
45 * D4.2.5 in the ARMv8-A Architecture Reference Manual (DDI 0487A.i) for more
46 * information.
47 */
48CASSERT(ADDR_SPACE_SIZE >= (1ull << 31) && ADDR_SPACE_SIZE <= (1ull << 39) &&
49 IS_POWER_OF_TWO(ADDR_SPACE_SIZE), assert_valid_addr_space_size);
50
51#define UNSET_DESC ~0ul
52#define NUM_L1_ENTRIES (ADDR_SPACE_SIZE >> L1_XLAT_ADDRESS_SHIFT)
53
54static uint64_t l1_xlation_table[NUM_L1_ENTRIES]
55 __aligned(NUM_L1_ENTRIES * sizeof(uint64_t));
56
57static unsigned long long tcr_ps_bits;
58
59static unsigned long long calc_physical_addr_size_bits(
60 unsigned long long max_addr)
61{
62 /* Physical address can't exceed 48 bits */
63 assert((max_addr & ADDR_MASK_48_TO_63) == 0);
64
65 /* 48 bits address */
66 if (max_addr & ADDR_MASK_44_TO_47)
67 return TCR_PS_BITS_256TB;
68
69 /* 44 bits address */
70 if (max_addr & ADDR_MASK_42_TO_43)
71 return TCR_PS_BITS_16TB;
72
73 /* 42 bits address */
74 if (max_addr & ADDR_MASK_40_TO_41)
75 return TCR_PS_BITS_4TB;
76
77 /* 40 bits address */
78 if (max_addr & ADDR_MASK_36_TO_39)
79 return TCR_PS_BITS_1TB;
80
81 /* 36 bits address */
82 if (max_addr & ADDR_MASK_32_TO_35)
83 return TCR_PS_BITS_64GB;
84
85 return TCR_PS_BITS_4GB;
86}
87
88void init_xlat_tables(void)
89{
90 unsigned long long max_pa;
91 uintptr_t max_va;
92 print_mmap();
93 init_xlation_table(0, l1_xlation_table, 1, &max_va, &max_pa);
94 tcr_ps_bits = calc_physical_addr_size_bits(max_pa);
95 assert(max_va < ADDR_SPACE_SIZE);
96}
97
98/*******************************************************************************
99 * Macro generating the code for the function enabling the MMU in the given
100 * exception level, assuming that the pagetables have already been created.
101 *
102 * _el: Exception level at which the function will run
103 * _tcr_extra: Extra bits to set in the TCR register. This mask will
104 * be OR'ed with the default TCR value.
105 * _tlbi_fct: Function to invalidate the TLBs at the current
106 * exception level
107 ******************************************************************************/
108#define DEFINE_ENABLE_MMU_EL(_el, _tcr_extra, _tlbi_fct) \
109 void enable_mmu_el##_el(unsigned int flags) \
110 { \
111 uint64_t mair, tcr, ttbr; \
112 uint32_t sctlr; \
113 \
114 assert(IS_IN_EL(_el)); \
115 assert((read_sctlr_el##_el() & SCTLR_M_BIT) == 0); \
116 \
117 /* Set attributes in the right indices of the MAIR */ \
118 mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); \
119 mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, \
120 ATTR_IWBWA_OWBWA_NTR_INDEX); \
121 mair |= MAIR_ATTR_SET(ATTR_NON_CACHEABLE, \
122 ATTR_NON_CACHEABLE_INDEX); \
123 write_mair_el##_el(mair); \
124 \
125 /* Invalidate TLBs at the current exception level */ \
126 _tlbi_fct(); \
127 \
128 /* Set TCR bits as well. */ \
129 /* Inner & outer WBWA & shareable + T0SZ = 32 */ \
130 tcr = TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WBA | \
131 TCR_RGN_INNER_WBA | \
132 (64 - __builtin_ctzl(ADDR_SPACE_SIZE)); \
133 tcr |= _tcr_extra; \
134 write_tcr_el##_el(tcr); \
135 \
136 /* Set TTBR bits as well */ \
137 ttbr = (uint64_t) l1_xlation_table; \
138 write_ttbr0_el##_el(ttbr); \
139 \
140 /* Ensure all translation table writes have drained */ \
141 /* into memory, the TLB invalidation is complete, */ \
142 /* and translation register writes are committed */ \
143 /* before enabling the MMU */ \
144 dsb(); \
145 isb(); \
146 \
147 sctlr = read_sctlr_el##_el(); \
148 sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; \
149 \
150 if (flags & DISABLE_DCACHE) \
151 sctlr &= ~SCTLR_C_BIT; \
152 else \
153 sctlr |= SCTLR_C_BIT; \
154 \
155 write_sctlr_el##_el(sctlr); \
156 \
157 /* Ensure the MMU enable takes effect immediately */ \
158 isb(); \
159 }
160
161/* Define EL1 and EL3 variants of the function enabling the MMU */
162DEFINE_ENABLE_MMU_EL(1,
163 (tcr_ps_bits << TCR_EL1_IPS_SHIFT),
164 tlbivmalle1)
165DEFINE_ENABLE_MMU_EL(3,
166 TCR_EL3_RES1 | (tcr_ps_bits << TCR_EL3_PS_SHIFT),
167 tlbialle3)