Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 1 | /* |
Antonio Nino Diaz | 4b32e62 | 2018-08-16 16:52:57 +0100 | [diff] [blame] | 2 | * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | 5a70094 | 2019-01-23 16:54:12 -0800 | [diff] [blame] | 3 | * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 4 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 5 | * SPDX-License-Identifier: BSD-3-Clause |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 6 | */ |
| 7 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 8 | #include <assert.h> |
| 9 | #include <errno.h> |
| 10 | #include <string.h> |
| 11 | |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 12 | #include <arch.h> |
| 13 | #include <arch_helpers.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 14 | #include <common/bl_common.h> |
| 15 | #include <common/debug.h> |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 16 | #include <context.h> |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 17 | #include <denver.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 18 | #include <lib/el3_runtime/context_mgmt.h> |
| 19 | #include <lib/mmio.h> |
| 20 | |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 21 | #include <mce.h> |
Varun Wadekar | b556828 | 2016-12-13 18:04:35 -0800 | [diff] [blame] | 22 | #include <mce_private.h> |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 23 | #include <t18x_ari.h> |
| 24 | #include <tegra_def.h> |
Varun Wadekar | efa66d4 | 2016-07-18 17:42:02 -0700 | [diff] [blame] | 25 | #include <tegra_platform.h> |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 26 | |
| 27 | /* NVG functions handlers */ |
| 28 | static arch_mce_ops_t nvg_mce_ops = { |
| 29 | .enter_cstate = nvg_enter_cstate, |
| 30 | .update_cstate_info = nvg_update_cstate_info, |
| 31 | .update_crossover_time = nvg_update_crossover_time, |
| 32 | .read_cstate_stats = nvg_read_cstate_stats, |
| 33 | .write_cstate_stats = nvg_write_cstate_stats, |
| 34 | .call_enum_misc = ari_enumeration_misc, |
| 35 | .is_ccx_allowed = nvg_is_ccx_allowed, |
| 36 | .is_sc7_allowed = nvg_is_sc7_allowed, |
| 37 | .online_core = nvg_online_core, |
| 38 | .cc3_ctrl = nvg_cc3_ctrl, |
| 39 | .update_reset_vector = ari_reset_vector_update, |
| 40 | .roc_flush_cache = ari_roc_flush_cache, |
| 41 | .roc_flush_cache_trbits = ari_roc_flush_cache_trbits, |
| 42 | .roc_clean_cache = ari_roc_clean_cache, |
| 43 | .read_write_mca = ari_read_write_mca, |
| 44 | .update_ccplex_gsc = ari_update_ccplex_gsc, |
Varun Wadekar | 4ff3e8d | 2016-04-29 10:40:02 -0700 | [diff] [blame] | 45 | .enter_ccplex_state = ari_enter_ccplex_state, |
Krishna Sitaraman | b429d56 | 2016-07-19 16:36:13 -0700 | [diff] [blame] | 46 | .read_write_uncore_perfmon = ari_read_write_uncore_perfmon, |
| 47 | .misc_ccplex = ari_misc_ccplex |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 48 | }; |
| 49 | |
| 50 | /* ARI functions handlers */ |
| 51 | static arch_mce_ops_t ari_mce_ops = { |
| 52 | .enter_cstate = ari_enter_cstate, |
| 53 | .update_cstate_info = ari_update_cstate_info, |
| 54 | .update_crossover_time = ari_update_crossover_time, |
| 55 | .read_cstate_stats = ari_read_cstate_stats, |
| 56 | .write_cstate_stats = ari_write_cstate_stats, |
| 57 | .call_enum_misc = ari_enumeration_misc, |
| 58 | .is_ccx_allowed = ari_is_ccx_allowed, |
| 59 | .is_sc7_allowed = ari_is_sc7_allowed, |
| 60 | .online_core = ari_online_core, |
| 61 | .cc3_ctrl = ari_cc3_ctrl, |
| 62 | .update_reset_vector = ari_reset_vector_update, |
| 63 | .roc_flush_cache = ari_roc_flush_cache, |
| 64 | .roc_flush_cache_trbits = ari_roc_flush_cache_trbits, |
| 65 | .roc_clean_cache = ari_roc_clean_cache, |
| 66 | .read_write_mca = ari_read_write_mca, |
| 67 | .update_ccplex_gsc = ari_update_ccplex_gsc, |
Varun Wadekar | 4ff3e8d | 2016-04-29 10:40:02 -0700 | [diff] [blame] | 68 | .enter_ccplex_state = ari_enter_ccplex_state, |
Krishna Sitaraman | b429d56 | 2016-07-19 16:36:13 -0700 | [diff] [blame] | 69 | .read_write_uncore_perfmon = ari_read_write_uncore_perfmon, |
| 70 | .misc_ccplex = ari_misc_ccplex |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 71 | }; |
| 72 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 73 | typedef struct { |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 74 | uint32_t ari_base; |
| 75 | arch_mce_ops_t *ops; |
| 76 | } mce_config_t; |
| 77 | |
| 78 | /* Table to hold the per-CPU ARI base address and function handlers */ |
| 79 | static mce_config_t mce_cfg_table[MCE_ARI_APERTURES_MAX] = { |
| 80 | { |
| 81 | /* A57 Core 0 */ |
| 82 | .ari_base = TEGRA_MMCRAB_BASE + MCE_ARI_APERTURE_0_OFFSET, |
| 83 | .ops = &ari_mce_ops, |
| 84 | }, |
| 85 | { |
| 86 | /* A57 Core 1 */ |
| 87 | .ari_base = TEGRA_MMCRAB_BASE + MCE_ARI_APERTURE_1_OFFSET, |
| 88 | .ops = &ari_mce_ops, |
| 89 | }, |
| 90 | { |
| 91 | /* A57 Core 2 */ |
| 92 | .ari_base = TEGRA_MMCRAB_BASE + MCE_ARI_APERTURE_2_OFFSET, |
| 93 | .ops = &ari_mce_ops, |
| 94 | }, |
| 95 | { |
| 96 | /* A57 Core 3 */ |
| 97 | .ari_base = TEGRA_MMCRAB_BASE + MCE_ARI_APERTURE_3_OFFSET, |
| 98 | .ops = &ari_mce_ops, |
| 99 | }, |
| 100 | { |
| 101 | /* D15 Core 0 */ |
| 102 | .ari_base = TEGRA_MMCRAB_BASE + MCE_ARI_APERTURE_4_OFFSET, |
| 103 | .ops = &nvg_mce_ops, |
| 104 | }, |
| 105 | { |
| 106 | /* D15 Core 1 */ |
| 107 | .ari_base = TEGRA_MMCRAB_BASE + MCE_ARI_APERTURE_5_OFFSET, |
| 108 | .ops = &nvg_mce_ops, |
| 109 | } |
| 110 | }; |
| 111 | |
| 112 | static uint32_t mce_get_curr_cpu_ari_base(void) |
| 113 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 114 | uint64_t mpidr = read_mpidr(); |
Anthony Zhou | 3b80450 | 2017-06-26 20:33:34 +0800 | [diff] [blame] | 115 | uint64_t cpuid = mpidr & MPIDR_CPU_MASK; |
| 116 | uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 117 | |
| 118 | /* |
| 119 | * T186 has 2 CPU clusters, one with Denver CPUs and the other with |
| 120 | * ARM CortexA-57 CPUs. Each cluster consists of 4 CPUs and the CPU |
| 121 | * numbers start from 0. In order to get the proper arch_mce_ops_t |
| 122 | * struct, we have to convert the Denver CPU ids to the corresponding |
| 123 | * indices in the mce_ops_table array. |
| 124 | */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 125 | if (impl == DENVER_IMPL) { |
| 126 | cpuid |= 0x4U; |
| 127 | } |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 128 | |
| 129 | return mce_cfg_table[cpuid].ari_base; |
| 130 | } |
| 131 | |
| 132 | static arch_mce_ops_t *mce_get_curr_cpu_ops(void) |
| 133 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 134 | uint64_t mpidr = read_mpidr(); |
Anthony Zhou | 3b80450 | 2017-06-26 20:33:34 +0800 | [diff] [blame] | 135 | uint64_t cpuid = mpidr & MPIDR_CPU_MASK; |
| 136 | uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & |
| 137 | MIDR_IMPL_MASK; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 138 | |
| 139 | /* |
| 140 | * T186 has 2 CPU clusters, one with Denver CPUs and the other with |
| 141 | * ARM CortexA-57 CPUs. Each cluster consists of 4 CPUs and the CPU |
| 142 | * numbers start from 0. In order to get the proper arch_mce_ops_t |
| 143 | * struct, we have to convert the Denver CPU ids to the corresponding |
| 144 | * indices in the mce_ops_table array. |
| 145 | */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 146 | if (impl == DENVER_IMPL) { |
| 147 | cpuid |= 0x4U; |
| 148 | } |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 149 | |
| 150 | return mce_cfg_table[cpuid].ops; |
| 151 | } |
| 152 | |
| 153 | /******************************************************************************* |
| 154 | * Common handler for all MCE commands |
| 155 | ******************************************************************************/ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 156 | int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 157 | uint64_t arg2) |
| 158 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 159 | const arch_mce_ops_t *ops; |
| 160 | gp_regs_t *gp_regs = get_gpregs_ctx(cm_get_context(NON_SECURE)); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 161 | uint32_t cpu_ari_base; |
| 162 | uint64_t ret64 = 0, arg3, arg4, arg5; |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 163 | int32_t ret = 0; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 164 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 165 | assert(gp_regs != NULL); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 166 | |
| 167 | /* get a pointer to the CPU's arch_mce_ops_t struct */ |
| 168 | ops = mce_get_curr_cpu_ops(); |
| 169 | |
| 170 | /* get the CPU's ARI base address */ |
| 171 | cpu_ari_base = mce_get_curr_cpu_ari_base(); |
| 172 | |
| 173 | switch (cmd) { |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 174 | case (uint64_t)MCE_CMD_ENTER_CSTATE: |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 175 | ret = ops->enter_cstate(cpu_ari_base, arg0, arg1); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 176 | |
| 177 | break; |
| 178 | |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 179 | case (uint64_t)MCE_CMD_UPDATE_CSTATE_INFO: |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 180 | /* |
| 181 | * get the parameters required for the update cstate info |
| 182 | * command |
| 183 | */ |
Anthony Zhou | 3b80450 | 2017-06-26 20:33:34 +0800 | [diff] [blame] | 184 | arg3 = read_ctx_reg(gp_regs, CTX_GPREG_X4); |
| 185 | arg4 = read_ctx_reg(gp_regs, CTX_GPREG_X5); |
| 186 | arg5 = read_ctx_reg(gp_regs, CTX_GPREG_X6); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 187 | |
| 188 | ret = ops->update_cstate_info(cpu_ari_base, (uint32_t)arg0, |
| 189 | (uint32_t)arg1, (uint32_t)arg2, (uint8_t)arg3, |
| 190 | (uint32_t)arg4, (uint8_t)arg5); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 191 | |
Anthony Zhou | 3b80450 | 2017-06-26 20:33:34 +0800 | [diff] [blame] | 192 | write_ctx_reg(gp_regs, CTX_GPREG_X4, (0ULL)); |
| 193 | write_ctx_reg(gp_regs, CTX_GPREG_X5, (0ULL)); |
| 194 | write_ctx_reg(gp_regs, CTX_GPREG_X6, (0ULL)); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 195 | |
| 196 | break; |
| 197 | |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 198 | case (uint64_t)MCE_CMD_UPDATE_CROSSOVER_TIME: |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 199 | ret = ops->update_crossover_time(cpu_ari_base, arg0, arg1); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 200 | |
| 201 | break; |
| 202 | |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 203 | case (uint64_t)MCE_CMD_READ_CSTATE_STATS: |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 204 | ret64 = ops->read_cstate_stats(cpu_ari_base, arg0); |
| 205 | |
| 206 | /* update context to return cstate stats value */ |
Anthony Zhou | 3b80450 | 2017-06-26 20:33:34 +0800 | [diff] [blame] | 207 | write_ctx_reg(gp_regs, CTX_GPREG_X1, (ret64)); |
| 208 | write_ctx_reg(gp_regs, CTX_GPREG_X2, (ret64)); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 209 | |
| 210 | break; |
| 211 | |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 212 | case (uint64_t)MCE_CMD_WRITE_CSTATE_STATS: |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 213 | ret = ops->write_cstate_stats(cpu_ari_base, arg0, arg1); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 214 | |
| 215 | break; |
| 216 | |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 217 | case (uint64_t)MCE_CMD_IS_CCX_ALLOWED: |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 218 | ret = ops->is_ccx_allowed(cpu_ari_base, arg0, arg1); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 219 | |
| 220 | /* update context to return CCx status value */ |
Anthony Zhou | 3b80450 | 2017-06-26 20:33:34 +0800 | [diff] [blame] | 221 | write_ctx_reg(gp_regs, CTX_GPREG_X1, (uint64_t)(ret)); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 222 | |
| 223 | break; |
| 224 | |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 225 | case (uint64_t)MCE_CMD_IS_SC7_ALLOWED: |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 226 | ret = ops->is_sc7_allowed(cpu_ari_base, arg0, arg1); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 227 | |
| 228 | /* update context to return SC7 status value */ |
Anthony Zhou | 3b80450 | 2017-06-26 20:33:34 +0800 | [diff] [blame] | 229 | write_ctx_reg(gp_regs, CTX_GPREG_X1, (uint64_t)(ret)); |
| 230 | write_ctx_reg(gp_regs, CTX_GPREG_X3, (uint64_t)(ret)); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 231 | |
| 232 | break; |
| 233 | |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 234 | case (uint64_t)MCE_CMD_ONLINE_CORE: |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 235 | ret = ops->online_core(cpu_ari_base, arg0); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 236 | |
| 237 | break; |
| 238 | |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 239 | case (uint64_t)MCE_CMD_CC3_CTRL: |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 240 | ret = ops->cc3_ctrl(cpu_ari_base, arg0, arg1, arg2); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 241 | |
| 242 | break; |
| 243 | |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 244 | case (uint64_t)MCE_CMD_ECHO_DATA: |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 245 | ret64 = ops->call_enum_misc(cpu_ari_base, TEGRA_ARI_MISC_ECHO, |
| 246 | arg0); |
| 247 | |
| 248 | /* update context to return if echo'd data matched source */ |
Anthony Zhou | 3b80450 | 2017-06-26 20:33:34 +0800 | [diff] [blame] | 249 | write_ctx_reg(gp_regs, CTX_GPREG_X1, ((ret64 == arg0) ? |
| 250 | 1ULL : 0ULL)); |
| 251 | write_ctx_reg(gp_regs, CTX_GPREG_X2, ((ret64 == arg0) ? |
| 252 | 1ULL : 0ULL)); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 253 | |
| 254 | break; |
| 255 | |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 256 | case (uint64_t)MCE_CMD_READ_VERSIONS: |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 257 | ret64 = ops->call_enum_misc(cpu_ari_base, TEGRA_ARI_MISC_VERSION, |
| 258 | arg0); |
| 259 | |
| 260 | /* |
| 261 | * version = minor(63:32) | major(31:0). Update context |
| 262 | * to return major and minor version number. |
| 263 | */ |
Anthony Zhou | 3b80450 | 2017-06-26 20:33:34 +0800 | [diff] [blame] | 264 | write_ctx_reg(gp_regs, CTX_GPREG_X1, (ret64)); |
| 265 | write_ctx_reg(gp_regs, CTX_GPREG_X2, (ret64 >> 32ULL)); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 266 | |
| 267 | break; |
| 268 | |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 269 | case (uint64_t)MCE_CMD_ENUM_FEATURES: |
Krishna Sitaraman | fc2ec16 | 2016-07-27 16:26:45 -0700 | [diff] [blame] | 270 | ret64 = ops->call_enum_misc(cpu_ari_base, |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 271 | TEGRA_ARI_MISC_FEATURE_LEAF_0, arg0); |
| 272 | |
| 273 | /* update context to return features value */ |
Anthony Zhou | 3b80450 | 2017-06-26 20:33:34 +0800 | [diff] [blame] | 274 | write_ctx_reg(gp_regs, CTX_GPREG_X1, (ret64)); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 275 | |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 276 | break; |
| 277 | |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 278 | case (uint64_t)MCE_CMD_ROC_FLUSH_CACHE_TRBITS: |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 279 | ret = ops->roc_flush_cache_trbits(cpu_ari_base); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 280 | |
| 281 | break; |
| 282 | |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 283 | case (uint64_t)MCE_CMD_ROC_FLUSH_CACHE: |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 284 | ret = ops->roc_flush_cache(cpu_ari_base); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 285 | |
| 286 | break; |
| 287 | |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 288 | case (uint64_t)MCE_CMD_ROC_CLEAN_CACHE: |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 289 | ret = ops->roc_clean_cache(cpu_ari_base); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 290 | |
| 291 | break; |
| 292 | |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 293 | case (uint64_t)MCE_CMD_ENUM_READ_MCA: |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 294 | ret64 = ops->read_write_mca(cpu_ari_base, arg0, &arg1); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 295 | |
| 296 | /* update context to return MCA data/error */ |
Anthony Zhou | 3b80450 | 2017-06-26 20:33:34 +0800 | [diff] [blame] | 297 | write_ctx_reg(gp_regs, CTX_GPREG_X1, (ret64)); |
| 298 | write_ctx_reg(gp_regs, CTX_GPREG_X2, (arg1)); |
| 299 | write_ctx_reg(gp_regs, CTX_GPREG_X3, (ret64)); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 300 | |
| 301 | break; |
| 302 | |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 303 | case (uint64_t)MCE_CMD_ENUM_WRITE_MCA: |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 304 | ret64 = ops->read_write_mca(cpu_ari_base, arg0, &arg1); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 305 | |
| 306 | /* update context to return MCA error */ |
Anthony Zhou | 3b80450 | 2017-06-26 20:33:34 +0800 | [diff] [blame] | 307 | write_ctx_reg(gp_regs, CTX_GPREG_X1, (ret64)); |
| 308 | write_ctx_reg(gp_regs, CTX_GPREG_X3, (ret64)); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 309 | |
| 310 | break; |
| 311 | |
Varun Wadekar | ad2824f | 2016-03-28 13:44:35 -0700 | [diff] [blame] | 312 | #if ENABLE_CHIP_VERIFICATION_HARNESS |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 313 | case (uint64_t)MCE_CMD_ENABLE_LATIC: |
Varun Wadekar | ad2824f | 2016-03-28 13:44:35 -0700 | [diff] [blame] | 314 | /* |
| 315 | * This call is not for production use. The constant value, |
| 316 | * 0xFFFF0000, is specific to allowing for enabling LATIC on |
| 317 | * pre-production parts for the chip verification harness. |
| 318 | * |
| 319 | * Enabling LATIC allows S/W to read the MINI ISPs in the |
| 320 | * CCPLEX. The ISMs are used for various measurements relevant |
| 321 | * to particular locations in the Silicon. They are small |
| 322 | * counters which can be polled to determine how fast a |
| 323 | * particular location in the Silicon is. |
| 324 | */ |
| 325 | ops->enter_ccplex_state(mce_get_curr_cpu_ari_base(), |
| 326 | 0xFFFF0000); |
| 327 | |
| 328 | break; |
| 329 | #endif |
Varun Wadekar | 4ff3e8d | 2016-04-29 10:40:02 -0700 | [diff] [blame] | 330 | |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 331 | case (uint64_t)MCE_CMD_UNCORE_PERFMON_REQ: |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 332 | ret = ops->read_write_uncore_perfmon(cpu_ari_base, arg0, &arg1); |
Varun Wadekar | 4ff3e8d | 2016-04-29 10:40:02 -0700 | [diff] [blame] | 333 | |
| 334 | /* update context to return data */ |
Anthony Zhou | 3b80450 | 2017-06-26 20:33:34 +0800 | [diff] [blame] | 335 | write_ctx_reg(gp_regs, CTX_GPREG_X1, (arg1)); |
Varun Wadekar | 4ff3e8d | 2016-04-29 10:40:02 -0700 | [diff] [blame] | 336 | break; |
| 337 | |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 338 | case (uint64_t)MCE_CMD_MISC_CCPLEX: |
Krishna Sitaraman | b429d56 | 2016-07-19 16:36:13 -0700 | [diff] [blame] | 339 | ops->misc_ccplex(cpu_ari_base, arg0, arg1); |
| 340 | |
| 341 | break; |
| 342 | |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 343 | default: |
Masahiro Yamada | e93a0f4 | 2018-02-02 15:09:36 +0900 | [diff] [blame] | 344 | ERROR("unknown MCE command (%llu)\n", cmd); |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 345 | ret = EINVAL; |
| 346 | break; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 347 | } |
| 348 | |
| 349 | return ret; |
| 350 | } |
| 351 | |
| 352 | /******************************************************************************* |
| 353 | * Handler to update the reset vector for CPUs |
| 354 | ******************************************************************************/ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 355 | int32_t mce_update_reset_vector(void) |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 356 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 357 | const arch_mce_ops_t *ops = mce_get_curr_cpu_ops(); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 358 | |
Krishna Sitaraman | d007f76 | 2016-09-02 16:53:04 -0700 | [diff] [blame] | 359 | ops->update_reset_vector(mce_get_curr_cpu_ari_base()); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 360 | |
| 361 | return 0; |
| 362 | } |
| 363 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 364 | static int32_t mce_update_ccplex_gsc(tegra_ari_gsc_index_t gsc_idx) |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 365 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 366 | const arch_mce_ops_t *ops = mce_get_curr_cpu_ops(); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 367 | |
| 368 | ops->update_ccplex_gsc(mce_get_curr_cpu_ari_base(), gsc_idx); |
| 369 | |
| 370 | return 0; |
| 371 | } |
| 372 | |
| 373 | /******************************************************************************* |
| 374 | * Handler to update carveout values for Video Memory Carveout region |
| 375 | ******************************************************************************/ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 376 | int32_t mce_update_gsc_videomem(void) |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 377 | { |
| 378 | return mce_update_ccplex_gsc(TEGRA_ARI_GSC_VPR_IDX); |
| 379 | } |
| 380 | |
| 381 | /******************************************************************************* |
| 382 | * Handler to update carveout values for TZDRAM aperture |
| 383 | ******************************************************************************/ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 384 | int32_t mce_update_gsc_tzdram(void) |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 385 | { |
| 386 | return mce_update_ccplex_gsc(TEGRA_ARI_GSC_TZ_DRAM_IDX); |
| 387 | } |
| 388 | |
| 389 | /******************************************************************************* |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 390 | * Handler to shutdown/reset the entire system |
| 391 | ******************************************************************************/ |
| 392 | __dead2 void mce_enter_ccplex_state(uint32_t state_idx) |
| 393 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 394 | const arch_mce_ops_t *ops = mce_get_curr_cpu_ops(); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 395 | |
| 396 | /* sanity check state value */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 397 | if ((state_idx != TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF) && |
| 398 | (state_idx != TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT)) { |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 399 | panic(); |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 400 | } |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 401 | |
| 402 | ops->enter_ccplex_state(mce_get_curr_cpu_ari_base(), state_idx); |
| 403 | |
| 404 | /* wait till the CCPLEX powers down */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 405 | for (;;) { |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 406 | ; |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 407 | } |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 408 | |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 409 | } |
Varun Wadekar | 47ddd00 | 2016-03-28 16:00:02 -0700 | [diff] [blame] | 410 | |
| 411 | /******************************************************************************* |
Varun Wadekar | c47504f | 2017-03-23 17:32:20 -0700 | [diff] [blame] | 412 | * Handler to issue the UPDATE_CSTATE_INFO request |
| 413 | ******************************************************************************/ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 414 | void mce_update_cstate_info(const mce_cstate_info_t *cstate) |
Varun Wadekar | c47504f | 2017-03-23 17:32:20 -0700 | [diff] [blame] | 415 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 416 | const arch_mce_ops_t *ops = mce_get_curr_cpu_ops(); |
Varun Wadekar | c47504f | 2017-03-23 17:32:20 -0700 | [diff] [blame] | 417 | |
| 418 | /* issue the UPDATE_CSTATE_INFO request */ |
| 419 | ops->update_cstate_info(mce_get_curr_cpu_ari_base(), cstate->cluster, |
| 420 | cstate->ccplex, cstate->system, cstate->system_state_force, |
| 421 | cstate->wake_mask, cstate->update_wake_mask); |
| 422 | } |
| 423 | |
| 424 | /******************************************************************************* |
Varun Wadekar | 47ddd00 | 2016-03-28 16:00:02 -0700 | [diff] [blame] | 425 | * Handler to read the MCE firmware version and check if it is compatible |
| 426 | * with interface header the BL3-1 was compiled against |
| 427 | ******************************************************************************/ |
| 428 | void mce_verify_firmware_version(void) |
| 429 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 430 | const arch_mce_ops_t *ops; |
Varun Wadekar | 47ddd00 | 2016-03-28 16:00:02 -0700 | [diff] [blame] | 431 | uint32_t cpu_ari_base; |
| 432 | uint64_t version; |
Varun Wadekar | efa66d4 | 2016-07-18 17:42:02 -0700 | [diff] [blame] | 433 | uint32_t major, minor; |
| 434 | |
| 435 | /* |
Varun Wadekar | b556828 | 2016-12-13 18:04:35 -0800 | [diff] [blame] | 436 | * MCE firmware is not supported on simulation platforms. |
Varun Wadekar | efa66d4 | 2016-07-18 17:42:02 -0700 | [diff] [blame] | 437 | */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 438 | if (tegra_platform_is_emulation()) { |
Varun Wadekar | 47ddd00 | 2016-03-28 16:00:02 -0700 | [diff] [blame] | 439 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 440 | INFO("MCE firmware is not supported\n"); |
Varun Wadekar | 47ddd00 | 2016-03-28 16:00:02 -0700 | [diff] [blame] | 441 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 442 | } else { |
| 443 | /* get a pointer to the CPU's arch_mce_ops_t struct */ |
| 444 | ops = mce_get_curr_cpu_ops(); |
Varun Wadekar | 47ddd00 | 2016-03-28 16:00:02 -0700 | [diff] [blame] | 445 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 446 | /* get the CPU's ARI base address */ |
| 447 | cpu_ari_base = mce_get_curr_cpu_ari_base(); |
Varun Wadekar | 47ddd00 | 2016-03-28 16:00:02 -0700 | [diff] [blame] | 448 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 449 | /* |
| 450 | * Read the MCE firmware version and extract the major and minor |
| 451 | * version fields |
| 452 | */ |
| 453 | version = ops->call_enum_misc(cpu_ari_base, TEGRA_ARI_MISC_VERSION, 0); |
| 454 | major = (uint32_t)version; |
| 455 | minor = (uint32_t)(version >> 32); |
Varun Wadekar | 47ddd00 | 2016-03-28 16:00:02 -0700 | [diff] [blame] | 456 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 457 | INFO("MCE Version - HW=%d:%d, SW=%d:%d\n", major, minor, |
| 458 | TEGRA_ARI_VERSION_MAJOR, TEGRA_ARI_VERSION_MINOR); |
Varun Wadekar | 47ddd00 | 2016-03-28 16:00:02 -0700 | [diff] [blame] | 459 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 460 | /* |
| 461 | * Verify that the MCE firmware version and the interface header |
| 462 | * match |
| 463 | */ |
| 464 | if (major != TEGRA_ARI_VERSION_MAJOR) { |
| 465 | ERROR("ARI major version mismatch\n"); |
| 466 | panic(); |
| 467 | } |
| 468 | |
| 469 | if (minor < TEGRA_ARI_VERSION_MINOR) { |
| 470 | ERROR("ARI minor version mismatch\n"); |
| 471 | panic(); |
| 472 | } |
Varun Wadekar | 47ddd00 | 2016-03-28 16:00:02 -0700 | [diff] [blame] | 473 | } |
| 474 | } |