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Chandni Cherukurif3a6cab2020-09-22 18:56:25 +05301#
Patrik Berglund541206a2022-09-14 17:22:15 +01002# Copyright (c) 2020-2023, Arm Limited. All rights reserved.
Chandni Cherukurif3a6cab2020-09-22 18:56:25 +05303#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
Manoj Kumarc7ea5f32021-08-26 10:56:16 +05307# Making sure the Morello platform type is specified
8ifeq ($(filter ${TARGET_PLATFORM}, fvp soc),)
9 $(error TARGET_PLATFORM must be fvp or soc)
10endif
11
Chandni Cherukurif3a6cab2020-09-22 18:56:25 +053012MORELLO_BASE := plat/arm/board/morello
13
14INTERCONNECT_SOURCES := ${MORELLO_BASE}/morello_interconnect.c
15
16PLAT_INCLUDES := -I${MORELLO_BASE}/include
17
18MORELLO_CPU_SOURCES := lib/cpus/aarch64/rainier.S
19
Chandni Cherukuric5a0c372020-10-01 10:11:44 +053020# GIC-600 configuration
21GICV3_SUPPORT_GIC600 := 1
22
23# Include GICv3 driver files
24include drivers/arm/gic/v3/gicv3.mk
25
26MORELLO_GIC_SOURCES := ${GICV3_SOURCES} \
Chandni Cherukurif3a6cab2020-09-22 18:56:25 +053027 plat/common/plat_gicv3.c \
28 plat/arm/common/arm_gicv3.c \
Chandni Cherukurif3a6cab2020-09-22 18:56:25 +053029
30PLAT_BL_COMMON_SOURCES := ${MORELLO_BASE}/morello_plat.c \
31 ${MORELLO_BASE}/aarch64/morello_helper.S
32
Manoj Kumar58876122021-01-10 16:12:24 +000033BL1_SOURCES := ${MORELLO_CPU_SOURCES} \
34 ${INTERCONNECT_SOURCES} \
35 ${MORELLO_BASE}/morello_err.c \
36 ${MORELLO_BASE}/morello_trusted_boot.c \
37 ${MORELLO_BASE}/morello_bl1_setup.c \
38 drivers/arm/sbsa/sbsa.c
39
40BL2_SOURCES := ${MORELLO_BASE}/morello_security.c \
41 ${MORELLO_BASE}/morello_err.c \
42 ${MORELLO_BASE}/morello_trusted_boot.c \
sah01066afc22021-11-18 10:04:27 +000043 ${MORELLO_BASE}/morello_bl2_setup.c \
44 ${MORELLO_BASE}/morello_image_load.c \
Manoj Kumar58876122021-01-10 16:12:24 +000045 lib/utils/mem_region.c \
sah01066afc22021-11-18 10:04:27 +000046 drivers/arm/css/sds/sds.c
Manoj Kumar58876122021-01-10 16:12:24 +000047
Chandni Cherukurif3a6cab2020-09-22 18:56:25 +053048BL31_SOURCES := ${MORELLO_CPU_SOURCES} \
49 ${INTERCONNECT_SOURCES} \
50 ${MORELLO_GIC_SOURCES} \
51 ${MORELLO_BASE}/morello_bl31_setup.c \
Werner Lewisb89b0862023-02-15 16:03:27 +000052 ${MORELLO_BASE}/morello_pm.c \
Chandni Cherukurif3a6cab2020-09-22 18:56:25 +053053 ${MORELLO_BASE}/morello_topology.c \
54 ${MORELLO_BASE}/morello_security.c \
55 drivers/arm/css/sds/sds.c
56
Manoj Kumar58876122021-01-10 16:12:24 +000057FDT_SOURCES += fdts/morello-${TARGET_PLATFORM}.dts \
58 ${MORELLO_BASE}/fdts/morello_fw_config.dts \
59 ${MORELLO_BASE}/fdts/morello_tb_fw_config.dts \
sah01066afc22021-11-18 10:04:27 +000060 ${MORELLO_BASE}/fdts/morello_nt_fw_config.dts
Manoj Kumar58876122021-01-10 16:12:24 +000061
62FW_CONFIG := ${BUILD_PLAT}/fdts/morello_fw_config.dtb
Patrik Berglund541206a2022-09-14 17:22:15 +010063HW_CONFIG := ${BUILD_PLAT}/fdts/morello-${TARGET_PLATFORM}.dtb
Manoj Kumar58876122021-01-10 16:12:24 +000064TB_FW_CONFIG := ${BUILD_PLAT}/fdts/morello_tb_fw_config.dtb
sah01066afc22021-11-18 10:04:27 +000065NT_FW_CONFIG := ${BUILD_PLAT}/fdts/morello_nt_fw_config.dtb
Manoj Kumar58876122021-01-10 16:12:24 +000066
67# Add the FW_CONFIG to FIP and specify the same to certtool
68$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
Patrik Berglund541206a2022-09-14 17:22:15 +010069# Add the HW_CONFIG to FIP and specify the same to certtool
70$(eval $(call TOOL_ADD_PAYLOAD,${HW_CONFIG},--hw-config,${HW_CONFIG}))
Manoj Kumar58876122021-01-10 16:12:24 +000071# Add the TB_FW_CONFIG to FIP and specify the same to certtool
72$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
sah01066afc22021-11-18 10:04:27 +000073# Add the NT_FW_CONFIG to FIP and specify the same to certtool
74$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG}))
Manoj Kumar58876122021-01-10 16:12:24 +000075
76MORELLO_FW_NVCTR_VAL := 0
77TFW_NVCTR_VAL := ${MORELLO_FW_NVCTR_VAL}
78NTFW_NVCTR_VAL := ${MORELLO_FW_NVCTR_VAL}
Chandni Cherukurif3a6cab2020-09-22 18:56:25 +053079
80# TF-A not required to load the SCP Images
81override CSS_LOAD_SCP_IMAGES := 0
82
Chandni Cherukurif3a6cab2020-09-22 18:56:25 +053083override NEED_BL2U := no
84
Chandni Cherukurif3a6cab2020-09-22 18:56:25 +053085# 32 bit mode not supported
86override CTX_INCLUDE_AARCH32_REGS := 0
87
88override ARM_PLAT_MT := 1
89
Manoj Kumar91162752022-06-23 12:30:37 +010090override ARM_BL31_IN_DRAM := 1
91
Manoj Kumar9f429332022-01-05 14:38:44 +000092# Errata workarounds:
93ERRATA_N1_1868343 := 1
94
Chandni Cherukurif3a6cab2020-09-22 18:56:25 +053095# Select SCMI/SDS drivers instead of SCPI/BOM driver for communicating with the
96# SCP during power management operations and for SCP RAM Firmware transfer.
97CSS_USE_SCMI_SDS_DRIVER := 1
98
99# System coherency is managed in hardware
100HW_ASSISTED_COHERENCY := 1
101
102# When building for systems with hardware-assisted coherency, there's no need to
103# use USE_COHERENT_MEM. Require that USE_COHERENT_MEM must be set to 0 too.
104USE_COHERENT_MEM := 0
105
Manoj Kumarc7ea5f32021-08-26 10:56:16 +0530106# Add TARGET_PLATFORM to differentiate between Morello FVP and Morello SoC platform
107$(eval $(call add_define,TARGET_PLATFORM_$(call uppercase,${TARGET_PLATFORM})))
108
Manoj Kumar58876122021-01-10 16:12:24 +0000109# Add MORELLO_FW_NVCTR_VAL
110$(eval $(call add_define,MORELLO_FW_NVCTR_VAL))
111
Chandni Cherukurif3a6cab2020-09-22 18:56:25 +0530112include plat/arm/common/arm_common.mk
113include plat/arm/css/common/css_common.mk
114include plat/arm/board/common/board_common.mk