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Achin Gupta7c88f3f2014-02-18 18:09:12 +00001/*
Daniel Boulby60786e72021-10-22 11:37:34 +01002 * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
Achin Gupta7c88f3f2014-02-18 18:09:12 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta7c88f3f2014-02-18 18:09:12 +00005 */
6
Alexei Fedorovf41355c2019-09-13 14:11:59 +01007#include <assert.h>
Scott Brandene5dcf982020-08-25 13:49:32 -07008#include <inttypes.h>
9#include <stdint.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010
Alexei Fedorovf41355c2019-09-13 14:11:59 +010011#include <arch_features.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000012#include <arch_helpers.h>
13#include <bl32/tsp/tsp.h>
14#include <common/bl_common.h>
15#include <common/debug.h>
16#include <lib/spinlock.h>
17#include <plat/common/platform.h>
Dan Handley4fd2f5c2014-08-04 11:41:20 +010018#include <platform_tsp.h>
Dan Handleye2c27f52014-08-01 17:58:27 +010019#include "tsp_private.h"
Achin Gupta7c88f3f2014-02-18 18:09:12 +000020
Achin Gupta6b4ec242021-10-04 20:13:36 +010021#include <platform_def.h>
Antonio Nino Diaze61ece02019-02-26 11:41:03 +000022
23/*******************************************************************************
Achin Gupta7c88f3f2014-02-18 18:09:12 +000024 * TSP main entry point where it gets the opportunity to initialize its secure
25 * state/applications. Once the state is initialized, it must return to the
Andrew Thoelke891c4ca2014-05-20 21:43:27 +010026 * SPD with a pointer to the 'tsp_vector_table' jump table.
Achin Gupta7c88f3f2014-02-18 18:09:12 +000027 ******************************************************************************/
28uint64_t tsp_main(void)
29{
Dan Handley91b624e2014-07-29 17:14:00 +010030 NOTICE("TSP: %s\n", version_string);
31 NOTICE("TSP: %s\n", build_message);
Sandrine Bailleuxbdba5e52016-06-16 14:24:26 +010032 INFO("TSP: Total memory base : 0x%lx\n", (unsigned long) BL32_BASE);
33 INFO("TSP: Total memory size : 0x%lx bytes\n", BL32_TOTAL_SIZE);
Dan Handley91b624e2014-07-29 17:14:00 +010034
Soby Mathewda43b662015-07-08 21:45:46 +010035 uint32_t linear_id = plat_my_core_pos();
Achin Gupta7c88f3f2014-02-18 18:09:12 +000036
Achin Gupta7c88f3f2014-02-18 18:09:12 +000037 /* Initialize the platform */
Dan Handley4fd2f5c2014-08-04 11:41:20 +010038 tsp_platform_setup();
Achin Gupta7c88f3f2014-02-18 18:09:12 +000039
40 /* Initialize secure/applications state here */
Achin Guptabbc33f22014-05-09 13:33:42 +010041 tsp_generic_timer_start();
Achin Gupta7c88f3f2014-02-18 18:09:12 +000042
43 /* Update this cpu's statistics */
44 tsp_stats[linear_id].smc_count++;
45 tsp_stats[linear_id].eret_count++;
46 tsp_stats[linear_id].cpu_on_count++;
47
Soby Mathewda43b662015-07-08 21:45:46 +010048 INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n",
49 read_mpidr(),
Achin Gupta7c88f3f2014-02-18 18:09:12 +000050 tsp_stats[linear_id].smc_count,
51 tsp_stats[linear_id].eret_count,
52 tsp_stats[linear_id].cpu_on_count);
Andrew Thoelke891c4ca2014-05-20 21:43:27 +010053 return (uint64_t) &tsp_vector_table;
Achin Gupta7c88f3f2014-02-18 18:09:12 +000054}
55
56/*******************************************************************************
57 * This function performs any remaining book keeping in the test secure payload
58 * after this cpu's architectural state has been setup in response to an earlier
59 * psci cpu_on request.
60 ******************************************************************************/
Achin Gupta6b4ec242021-10-04 20:13:36 +010061smc_args_t *tsp_cpu_on_main(void)
Achin Gupta7c88f3f2014-02-18 18:09:12 +000062{
Soby Mathewda43b662015-07-08 21:45:46 +010063 uint32_t linear_id = plat_my_core_pos();
Achin Gupta7c88f3f2014-02-18 18:09:12 +000064
Achin Guptabbc33f22014-05-09 13:33:42 +010065 /* Initialize secure/applications state here */
66 tsp_generic_timer_start();
67
Achin Gupta7c88f3f2014-02-18 18:09:12 +000068 /* Update this cpu's statistics */
69 tsp_stats[linear_id].smc_count++;
70 tsp_stats[linear_id].eret_count++;
71 tsp_stats[linear_id].cpu_on_count++;
72
Soby Mathewda43b662015-07-08 21:45:46 +010073 INFO("TSP: cpu 0x%lx turned on\n", read_mpidr());
74 INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n",
75 read_mpidr(),
Dan Handley91b624e2014-07-29 17:14:00 +010076 tsp_stats[linear_id].smc_count,
77 tsp_stats[linear_id].eret_count,
78 tsp_stats[linear_id].cpu_on_count);
Achin Gupta7c88f3f2014-02-18 18:09:12 +000079 /* Indicate to the SPD that we have completed turned ourselves on */
80 return set_smc_args(TSP_ON_DONE, 0, 0, 0, 0, 0, 0, 0);
81}
82
83/*******************************************************************************
84 * This function performs any remaining book keeping in the test secure payload
85 * before this cpu is turned off in response to a psci cpu_off request.
86 ******************************************************************************/
Achin Gupta6b4ec242021-10-04 20:13:36 +010087smc_args_t *tsp_cpu_off_main(uint64_t arg0,
Achin Gupta7c88f3f2014-02-18 18:09:12 +000088 uint64_t arg1,
89 uint64_t arg2,
90 uint64_t arg3,
91 uint64_t arg4,
92 uint64_t arg5,
93 uint64_t arg6,
94 uint64_t arg7)
95{
Soby Mathewda43b662015-07-08 21:45:46 +010096 uint32_t linear_id = plat_my_core_pos();
Achin Gupta7c88f3f2014-02-18 18:09:12 +000097
Achin Guptabbc33f22014-05-09 13:33:42 +010098 /*
99 * This cpu is being turned off, so disable the timer to prevent the
100 * secure timer interrupt from interfering with power down. A pending
101 * interrupt will be lost but we do not care as we are turning off.
102 */
103 tsp_generic_timer_stop();
104
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000105 /* Update this cpu's statistics */
106 tsp_stats[linear_id].smc_count++;
107 tsp_stats[linear_id].eret_count++;
108 tsp_stats[linear_id].cpu_off_count++;
109
Soby Mathewda43b662015-07-08 21:45:46 +0100110 INFO("TSP: cpu 0x%lx off request\n", read_mpidr());
111 INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu off requests\n",
112 read_mpidr(),
Dan Handley91b624e2014-07-29 17:14:00 +0100113 tsp_stats[linear_id].smc_count,
114 tsp_stats[linear_id].eret_count,
115 tsp_stats[linear_id].cpu_off_count);
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000116
Achin Gupta607084e2014-02-09 18:24:19 +0000117 /* Indicate to the SPD that we have completed this request */
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000118 return set_smc_args(TSP_OFF_DONE, 0, 0, 0, 0, 0, 0, 0);
119}
120
121/*******************************************************************************
122 * This function performs any book keeping in the test secure payload before
123 * this cpu's architectural state is saved in response to an earlier psci
124 * cpu_suspend request.
125 ******************************************************************************/
Achin Gupta6b4ec242021-10-04 20:13:36 +0100126smc_args_t *tsp_cpu_suspend_main(uint64_t arg0,
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000127 uint64_t arg1,
128 uint64_t arg2,
129 uint64_t arg3,
130 uint64_t arg4,
131 uint64_t arg5,
132 uint64_t arg6,
133 uint64_t arg7)
134{
Soby Mathewda43b662015-07-08 21:45:46 +0100135 uint32_t linear_id = plat_my_core_pos();
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000136
Achin Guptabbc33f22014-05-09 13:33:42 +0100137 /*
138 * Save the time context and disable it to prevent the secure timer
139 * interrupt from interfering with wakeup from the suspend state.
140 */
141 tsp_generic_timer_save();
142 tsp_generic_timer_stop();
143
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000144 /* Update this cpu's statistics */
145 tsp_stats[linear_id].smc_count++;
146 tsp_stats[linear_id].eret_count++;
147 tsp_stats[linear_id].cpu_suspend_count++;
148
Sandrine Bailleux8723adf2015-02-05 15:42:31 +0000149 INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu suspend requests\n",
Soby Mathewda43b662015-07-08 21:45:46 +0100150 read_mpidr(),
Dan Handley91b624e2014-07-29 17:14:00 +0100151 tsp_stats[linear_id].smc_count,
152 tsp_stats[linear_id].eret_count,
153 tsp_stats[linear_id].cpu_suspend_count);
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000154
Achin Gupta607084e2014-02-09 18:24:19 +0000155 /* Indicate to the SPD that we have completed this request */
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000156 return set_smc_args(TSP_SUSPEND_DONE, 0, 0, 0, 0, 0, 0, 0);
157}
158
159/*******************************************************************************
160 * This function performs any book keeping in the test secure payload after this
161 * cpu's architectural state has been restored after wakeup from an earlier psci
162 * cpu_suspend request.
163 ******************************************************************************/
Achin Gupta6b4ec242021-10-04 20:13:36 +0100164smc_args_t *tsp_cpu_resume_main(uint64_t max_off_pwrlvl,
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000165 uint64_t arg1,
166 uint64_t arg2,
167 uint64_t arg3,
168 uint64_t arg4,
169 uint64_t arg5,
170 uint64_t arg6,
171 uint64_t arg7)
172{
Soby Mathewda43b662015-07-08 21:45:46 +0100173 uint32_t linear_id = plat_my_core_pos();
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000174
Achin Guptabbc33f22014-05-09 13:33:42 +0100175 /* Restore the generic timer context */
176 tsp_generic_timer_restore();
177
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000178 /* Update this cpu's statistics */
179 tsp_stats[linear_id].smc_count++;
180 tsp_stats[linear_id].eret_count++;
181 tsp_stats[linear_id].cpu_resume_count++;
182
Scott Brandene5dcf982020-08-25 13:49:32 -0700183 INFO("TSP: cpu 0x%lx resumed. maximum off power level %" PRId64 "\n",
Achin Gupta9a0ff9b2015-09-07 20:43:27 +0100184 read_mpidr(), max_off_pwrlvl);
Manish Pandeyc4b47a22020-03-06 14:36:25 +0000185 INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu resume requests\n",
Soby Mathewda43b662015-07-08 21:45:46 +0100186 read_mpidr(),
Dan Handley91b624e2014-07-29 17:14:00 +0100187 tsp_stats[linear_id].smc_count,
188 tsp_stats[linear_id].eret_count,
Manish Pandeyc4b47a22020-03-06 14:36:25 +0000189 tsp_stats[linear_id].cpu_resume_count);
Achin Gupta607084e2014-02-09 18:24:19 +0000190 /* Indicate to the SPD that we have completed this request */
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000191 return set_smc_args(TSP_RESUME_DONE, 0, 0, 0, 0, 0, 0, 0);
192}
193
194/*******************************************************************************
195 * TSP fast smc handler. The secure monitor jumps to this function by
196 * doing the ERET after populating X0-X7 registers. The arguments are received
197 * in the function arguments in order. Once the service is rendered, this
Soby Mathew9f71f702014-05-09 20:49:17 +0100198 * function returns to Secure Monitor by raising SMC.
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000199 ******************************************************************************/
Achin Gupta6b4ec242021-10-04 20:13:36 +0100200smc_args_t *tsp_smc_handler(uint64_t func,
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000201 uint64_t arg1,
202 uint64_t arg2,
203 uint64_t arg3,
204 uint64_t arg4,
205 uint64_t arg5,
206 uint64_t arg6,
207 uint64_t arg7)
208{
Alexei Fedorov7d616ee2020-11-13 12:36:49 +0000209 uint128_t service_args;
210 uint64_t service_arg0;
211 uint64_t service_arg1;
Achin Gupta916a2c12014-02-09 23:11:46 +0000212 uint64_t results[2];
Soby Mathewda43b662015-07-08 21:45:46 +0100213 uint32_t linear_id = plat_my_core_pos();
Daniel Boulby60786e72021-10-22 11:37:34 +0100214 u_register_t dit;
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000215
Achin Gupta916a2c12014-02-09 23:11:46 +0000216 /* Update this cpu's statistics */
217 tsp_stats[linear_id].smc_count++;
218 tsp_stats[linear_id].eret_count++;
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000219
Scott Brandene5dcf982020-08-25 13:49:32 -0700220 INFO("TSP: cpu 0x%lx received %s smc 0x%" PRIx64 "\n", read_mpidr(),
David Cunado28f69ab2017-04-05 11:34:03 +0100221 ((func >> 31) & 1) == 1 ? "fast" : "yielding",
Dan Handley91b624e2014-07-29 17:14:00 +0100222 func);
Soby Mathewda43b662015-07-08 21:45:46 +0100223 INFO("TSP: cpu 0x%lx: %d smcs, %d erets\n", read_mpidr(),
Dan Handley91b624e2014-07-29 17:14:00 +0100224 tsp_stats[linear_id].smc_count,
225 tsp_stats[linear_id].eret_count);
Achin Gupta916a2c12014-02-09 23:11:46 +0000226
227 /* Render secure services and obtain results here */
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000228 results[0] = arg1;
229 results[1] = arg2;
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000230
231 /*
Alexei Fedorov7d616ee2020-11-13 12:36:49 +0000232 * Request a service back from dispatcher/secure monitor.
233 * This call returns and thereafter resumes execution.
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000234 */
Alexei Fedorov7d616ee2020-11-13 12:36:49 +0000235 service_args = tsp_get_magic();
236 service_arg0 = (uint64_t)service_args;
237 service_arg1 = (uint64_t)(service_args >> 64U);
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000238
Justin Chadwell1c7c13a2019-07-18 14:25:33 +0100239#if CTX_INCLUDE_MTE_REGS
240 /*
241 * Write a dummy value to an MTE register, to simulate usage in the
242 * secure world
243 */
244 write_gcr_el1(0x99);
245#endif
246
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000247 /* Determine the function to perform based on the function ID */
Soby Mathew9f71f702014-05-09 20:49:17 +0100248 switch (TSP_BARE_FID(func)) {
249 case TSP_ADD:
Alexei Fedorov7d616ee2020-11-13 12:36:49 +0000250 results[0] += service_arg0;
251 results[1] += service_arg1;
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000252 break;
Soby Mathew9f71f702014-05-09 20:49:17 +0100253 case TSP_SUB:
Alexei Fedorov7d616ee2020-11-13 12:36:49 +0000254 results[0] -= service_arg0;
255 results[1] -= service_arg1;
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000256 break;
Soby Mathew9f71f702014-05-09 20:49:17 +0100257 case TSP_MUL:
Alexei Fedorov7d616ee2020-11-13 12:36:49 +0000258 results[0] *= service_arg0;
259 results[1] *= service_arg1;
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000260 break;
Soby Mathew9f71f702014-05-09 20:49:17 +0100261 case TSP_DIV:
Alexei Fedorov7d616ee2020-11-13 12:36:49 +0000262 results[0] /= service_arg0 ? service_arg0 : 1;
263 results[1] /= service_arg1 ? service_arg1 : 1;
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000264 break;
Daniel Boulby60786e72021-10-22 11:37:34 +0100265 case TSP_CHECK_DIT:
266 if (!is_armv8_4_dit_present()) {
Daniel Boulby60786e72021-10-22 11:37:34 +0100267 ERROR("DIT not supported\n");
Daniel Boulby60786e72021-10-22 11:37:34 +0100268 results[0] = 0;
269 results[1] = 0xffff;
270 break;
271 }
272 dit = read_dit();
273 results[0] = dit == service_arg0;
274 results[1] = dit;
275 /* Toggle the dit bit */
276 write_dit(service_arg0 != 0U ? 0 : DIT_BIT);
277 break;
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000278 default:
279 break;
280 }
281
Soby Mathew9f71f702014-05-09 20:49:17 +0100282 return set_smc_args(func, 0,
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000283 results[0],
284 results[1],
Soby Mathew9f71f702014-05-09 20:49:17 +0100285 0, 0, 0, 0);
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000286}