blob: 4b8a0d182833b4cc0944c4feddfaa2f2197fb11c [file] [log] [blame]
Sughosh Ganu18f513d2018-05-16 17:22:35 +05301/*
Thomas Abraham12c6a5a2021-02-16 12:24:13 +05302 * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
Sughosh Ganu18f513d2018-05-16 17:22:35 +05303 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef SGI_RAS_H
8#define SGI_RAS_H
Sughosh Ganu18f513d2018-05-16 17:22:35 +05309
Thomas Abraham12c6a5a2021-02-16 12:24:13 +053010/* Platform specific SMC FID's used for DMC-620 RAS error handling */
11#define SP_DMC_ERROR_OVERFLOW_EVENT_AARCH64 0xC4000043
12#define SP_DMC_ERROR_ECC_EVENT_AARCH64 0xC4000044
13
Sughosh Ganu18f513d2018-05-16 17:22:35 +053014/*
15 * Mapping the RAS interrupt with SDEI event number and the event
16 * id used with Standalone MM code
17 */
18struct sgi_ras_ev_map {
19 int ras_ev_num; /* RAS Event number */
20 int sdei_ev_num; /* SDEI Event number */
21 int intr; /* Physical intr number */
22};
23
24int sgi_ras_intr_handler_setup(void);
25
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +000026#endif /* SGI_RAS_H */