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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Achin Gupta4f6ad662013-10-25 09:08:21 +010031#include <assert.h>
32#include <arch_helpers.h>
James Morrissey40a6f642014-02-10 14:24:36 +000033#include "debug.h"
Jon Medhurstb1eb0932014-02-26 16:27:53 +000034#include <platform.h>
35#include <xlat_tables.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010036
37unsigned char platform_normal_stacks[PLATFORM_STACK_SIZE][PLATFORM_CORE_COUNT]
38__attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE),
39 section("tzfw_normal_stacks")));
40
41/*******************************************************************************
42 * This array holds the characteristics of the differences between the three
43 * FVP platforms (Base, A53_A57 & Foundation). It will be populated during cold
44 * boot at each boot stage by the primary before enabling the MMU (to allow cci
45 * configuration) & used thereafter. Each BL will have its own copy to allow
46 * independent operation.
47 ******************************************************************************/
48static unsigned long platform_config[CONFIG_LIMIT];
49
50/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +010051 * Enable the MMU assuming that the pagetables have already been created
52 *******************************************************************************/
53void enable_mmu()
54{
55 unsigned long mair, tcr, ttbr, sctlr;
56 unsigned long current_el = read_current_el();
57
58 /* Set the attributes in the right indices of the MAIR */
59 mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX);
60 mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR,
61 ATTR_IWBWA_OWBWA_NTR_INDEX);
62 write_mair(mair);
63
64 /*
65 * Set TCR bits as well. Inner & outer WBWA & shareable + T0SZ = 32
66 */
67 tcr = TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WBA |
68 TCR_RGN_INNER_WBA | TCR_T0SZ_4GB;
69 if (GET_EL(current_el) == MODE_EL3) {
70 tcr |= TCR_EL3_RES1;
Sandrine Bailleux295538b2013-11-15 14:46:44 +000071 /* Invalidate EL3 TLBs */
Achin Gupta4f6ad662013-10-25 09:08:21 +010072 tlbialle3();
73 } else {
74 /* Invalidate EL1 TLBs */
75 tlbivmalle1();
76 }
77
78 write_tcr(tcr);
79
Jon Medhurstb1eb0932014-02-26 16:27:53 +000080 /* Set TTBR bits as well */
Achin Gupta4f6ad662013-10-25 09:08:21 +010081 ttbr = (unsigned long) l1_xlation_table;
82 write_ttbr0(ttbr);
83
84 sctlr = read_sctlr();
85 sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT | SCTLR_I_BIT;
86 sctlr |= SCTLR_A_BIT | SCTLR_C_BIT;
87 write_sctlr(sctlr);
88
89 return;
90}
91
92void disable_mmu(void)
93{
Vikram Kanigirica0aeb72014-03-20 12:23:21 +000094 unsigned long sctlr;
95
96 sctlr = read_sctlr();
97 sctlr = sctlr & ~(SCTLR_M_BIT | SCTLR_C_BIT);
98 write_sctlr(sctlr);
Achin Gupta4f6ad662013-10-25 09:08:21 +010099
Achin Gupta4f6ad662013-10-25 09:08:21 +0100100 /* Flush the caches */
101 dcsw_op_all(DCCISW);
102
103 return;
104}
105
Jon Medhurstb1eb0932014-02-26 16:27:53 +0000106/*
107 * Table of regions to map using the MMU.
108 * This doesn't include TZRAM as the 'mem_layout' argument passed to to
109 * configure_mmu() will give the available subset of that,
110 */
111const mmap_region mmap[] = {
112 { TZROM_BASE, TZROM_SIZE, MT_MEMORY | MT_RO | MT_SECURE },
113 { TZDRAM_BASE, TZDRAM_SIZE, MT_MEMORY | MT_RW | MT_SECURE },
114 { FLASH0_BASE, FLASH0_SIZE, MT_MEMORY | MT_RO | MT_SECURE },
115 { FLASH1_BASE, FLASH1_SIZE, MT_MEMORY | MT_RO | MT_SECURE },
116 { VRAM_BASE, VRAM_SIZE, MT_MEMORY | MT_RW | MT_SECURE },
117 { DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE },
118 { NSRAM_BASE, NSRAM_SIZE, MT_MEMORY | MT_RW | MT_NS },
119 { DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE },
120 /* 2nd GB as device for now...*/
121 { 0x40000000, 0x40000000, MT_DEVICE | MT_RW | MT_SECURE },
122 { DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS },
123 {0}
124};
125
Achin Gupta4f6ad662013-10-25 09:08:21 +0100126/*******************************************************************************
127 * Setup the pagetables as per the platform memory map & initialize the mmu
128 *******************************************************************************/
129void configure_mmu(meminfo *mem_layout,
130 unsigned long ro_start,
131 unsigned long ro_limit,
132 unsigned long coh_start,
133 unsigned long coh_limit)
134{
Jon Medhurstb1eb0932014-02-26 16:27:53 +0000135 mmap_add_region(mem_layout->total_base, mem_layout->total_size,
136 MT_MEMORY | MT_RW | MT_SECURE);
137 mmap_add_region(ro_start, ro_limit - ro_start,
138 MT_MEMORY | MT_RO | MT_SECURE);
139 mmap_add_region(coh_start, coh_limit - coh_start,
140 MT_DEVICE | MT_RW | MT_SECURE);
141
142 mmap_add(mmap);
143
144 init_xlat_tables();
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000145
Achin Gupta4f6ad662013-10-25 09:08:21 +0100146 enable_mmu();
147 return;
148}
149
150/* Simple routine which returns a configuration variable value */
151unsigned long platform_get_cfgvar(unsigned int var_id)
152{
153 assert(var_id < CONFIG_LIMIT);
154 return platform_config[var_id];
155}
156
157/*******************************************************************************
158 * A single boot loader stack is expected to work on both the Foundation FVP
159 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The
160 * SYS_ID register provides a mechanism for detecting the differences between
161 * these platforms. This information is stored in a per-BL array to allow the
162 * code to take the correct path.Per BL platform configuration.
163 ******************************************************************************/
164int platform_config_setup(void)
165{
166 unsigned int rev, hbi, bld, arch, sys_id, midr_pn;
167
168 sys_id = mmio_read_32(VE_SYSREGS_BASE + V2M_SYS_ID);
169 rev = (sys_id >> SYS_ID_REV_SHIFT) & SYS_ID_REV_MASK;
170 hbi = (sys_id >> SYS_ID_HBI_SHIFT) & SYS_ID_HBI_MASK;
171 bld = (sys_id >> SYS_ID_BLD_SHIFT) & SYS_ID_BLD_MASK;
172 arch = (sys_id >> SYS_ID_ARCH_SHIFT) & SYS_ID_ARCH_MASK;
173
James Morrissey40a6f642014-02-10 14:24:36 +0000174 if ((rev != REV_FVP) || (arch != ARCH_MODEL))
175 panic();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100176
177 /*
178 * The build field in the SYS_ID tells which variant of the GIC
179 * memory is implemented by the model.
180 */
181 switch (bld) {
182 case BLD_GIC_VE_MMAP:
183 platform_config[CONFIG_GICD_ADDR] = VE_GICD_BASE;
184 platform_config[CONFIG_GICC_ADDR] = VE_GICC_BASE;
185 platform_config[CONFIG_GICH_ADDR] = VE_GICH_BASE;
186 platform_config[CONFIG_GICV_ADDR] = VE_GICV_BASE;
187 break;
188 case BLD_GIC_A53A57_MMAP:
189 platform_config[CONFIG_GICD_ADDR] = BASE_GICD_BASE;
190 platform_config[CONFIG_GICC_ADDR] = BASE_GICC_BASE;
191 platform_config[CONFIG_GICH_ADDR] = BASE_GICH_BASE;
192 platform_config[CONFIG_GICV_ADDR] = BASE_GICV_BASE;
193 break;
194 default:
195 assert(0);
196 }
197
198 /*
199 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010
200 * for the Foundation FVP.
201 */
202 switch (hbi) {
203 case HBI_FOUNDATION:
204 platform_config[CONFIG_MAX_AFF0] = 4;
205 platform_config[CONFIG_MAX_AFF1] = 1;
206 platform_config[CONFIG_CPU_SETUP] = 0;
207 platform_config[CONFIG_BASE_MMAP] = 0;
Harry Liebel30affd52013-10-30 17:41:48 +0000208 platform_config[CONFIG_HAS_CCI] = 0;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100209 break;
210 case HBI_FVP_BASE:
211 midr_pn = (read_midr() >> MIDR_PN_SHIFT) & MIDR_PN_MASK;
212 if ((midr_pn == MIDR_PN_A57) || (midr_pn == MIDR_PN_A53))
213 platform_config[CONFIG_CPU_SETUP] = 1;
214 else
215 platform_config[CONFIG_CPU_SETUP] = 0;
216
217 platform_config[CONFIG_MAX_AFF0] = 4;
218 platform_config[CONFIG_MAX_AFF1] = 2;
219 platform_config[CONFIG_BASE_MMAP] = 1;
Harry Liebel30affd52013-10-30 17:41:48 +0000220 platform_config[CONFIG_HAS_CCI] = 1;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100221 break;
222 default:
223 assert(0);
224 }
225
226 return 0;
227}
228
Ian Spray84687392014-01-02 16:57:12 +0000229unsigned long plat_get_ns_image_entrypoint(void)
230{
Achin Gupta4f6ad662013-10-25 09:08:21 +0100231 return NS_IMAGE_OFFSET;
232}