blob: 996dedcb5c9702c0edb3702f7fa698a20ae3fe1c [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
Dan Handley714a0d22014-04-09 13:13:04 +010032#include <asm_macros.S>
Dan Handley2bd4ef22014-04-09 13:14:54 +010033#include <context.h>
Achin Gupta9cf2bb72014-05-09 11:07:09 +010034#include <interrupt_mgmt.h>
Dan Handleyed6ff952014-05-14 17:44:19 +010035#include <platform_def.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010036#include <runtime_svc.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010037
38 .globl runtime_exceptions
Jeenu Viswambharancaa84932014-02-06 10:36:15 +000039 .globl el3_exit
Achin Gupta4f6ad662013-10-25 09:08:21 +010040
Achin Gupta9cf2bb72014-05-09 11:07:09 +010041 /* -----------------------------------------------------
42 * Handle SMC exceptions seperately from other sync.
43 * exceptions.
44 * -----------------------------------------------------
45 */
46 .macro handle_sync_exception
47 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
48 mrs x30, esr_el3
49 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
50
51 cmp x30, #EC_AARCH32_SMC
52 b.eq smc_handler32
53
54 cmp x30, #EC_AARCH64_SMC
55 b.eq smc_handler64
56
57 /* -----------------------------------------------------
58 * The following code handles any synchronous exception
59 * that is not an SMC.
60 * -----------------------------------------------------
61 */
62
Soby Mathewc1adbbc2014-06-25 10:07:40 +010063 bl report_unhandled_exception
Achin Gupta9cf2bb72014-05-09 11:07:09 +010064 .endm
65
66
67 /* -----------------------------------------------------
68 * This macro handles FIQ or IRQ interrupts i.e. EL3,
69 * S-EL1 and NS interrupts.
70 * -----------------------------------------------------
71 */
72 .macro handle_interrupt_exception label
73 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
74 bl save_gp_registers
75
76 /* Switch to the runtime stack i.e. SP_EL0 */
77 ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
78 mov x20, sp
79 msr spsel, #0
80 mov sp, x2
81
82 /*
83 * Find out whether this is a valid interrupt type. If the
84 * interrupt controller reports a spurious interrupt then
85 * return to where we came from.
86 */
Dan Handley701fea72014-05-27 16:17:21 +010087 bl plat_ic_get_pending_interrupt_type
Achin Gupta9cf2bb72014-05-09 11:07:09 +010088 cmp x0, #INTR_TYPE_INVAL
89 b.eq interrupt_exit_\label
90
91 /*
92 * Get the registered handler for this interrupt type. A
93 * NULL return value implies that an interrupt was generated
94 * for which there is no handler registered or the interrupt
95 * was routed incorrectly. This is a problem of the framework
96 * so report it as an error.
97 */
98 bl get_interrupt_type_handler
99 cbz x0, interrupt_error_\label
100 mov x21, x0
101
102 mov x0, #INTR_ID_UNAVAILABLE
103#if IMF_READ_INTERRUPT_ID
104 /*
105 * Read the id of the highest priority pending interrupt. If
106 * no interrupt is asserted then return to where we came from.
107 */
Soby Mathew93c89ec2014-05-28 17:14:36 +0100108 mov x19, #INTR_ID_UNAVAILABLE
Dan Handley701fea72014-05-27 16:17:21 +0100109 bl plat_ic_get_pending_interrupt_id
Soby Mathew93c89ec2014-05-28 17:14:36 +0100110 cmp x19, x0
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100111 b.eq interrupt_exit_\label
112#endif
113
114 /*
115 * Save the EL3 system registers needed to return from
116 * this exception.
117 */
118 mrs x3, spsr_el3
119 mrs x4, elr_el3
120 stp x3, x4, [x20, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
121
122 /* Set the current security state in the 'flags' parameter */
123 mrs x2, scr_el3
124 ubfx x1, x2, #0, #1
125
126 /* Restore the reference to the 'handle' i.e. SP_EL3 */
127 mov x2, x20
128
Soby Mathew799f0ab2014-05-27 16:54:31 +0100129 /* x3 will point to a cookie (not used now) */
130 mov x3, xzr
131
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100132 /* Call the interrupt type handler */
133 blr x21
134
135interrupt_exit_\label:
136 /* Return from exception, possibly in a different security state */
137 b el3_exit
138
139 /*
140 * This label signifies a problem with the interrupt management
141 * framework where it is not safe to go back to the instruction
142 * where the interrupt was generated.
143 */
144interrupt_error_\label:
Soby Mathewc1adbbc2014-06-25 10:07:40 +0100145 bl report_unhandled_interrupt
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100146 .endm
147
148
Soby Mathew6c5192a2014-04-30 15:36:37 +0100149 .macro save_x18_to_x29_sp_el0
150 stp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18]
151 stp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20]
152 stp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22]
153 stp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24]
154 stp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26]
155 stp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
156 mrs x18, sp_el0
157 str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0]
158 .endm
159
Achin Guptab739f222014-01-18 16:50:09 +0000160 .section .vectors, "ax"; .align 11
Achin Gupta4f6ad662013-10-25 09:08:21 +0100161 .align 7
162runtime_exceptions:
163 /* -----------------------------------------------------
164 * Current EL with _sp_el0 : 0x0 - 0x180
165 * -----------------------------------------------------
166 */
167sync_exception_sp_el0:
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000168 /* -----------------------------------------------------
169 * We don't expect any synchronous exceptions from EL3
170 * -----------------------------------------------------
171 */
Soby Mathewc1adbbc2014-06-25 10:07:40 +0100172 bl report_unhandled_exception
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000173 check_vector_size sync_exception_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100174
175 .align 7
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000176 /* -----------------------------------------------------
177 * EL3 code is non-reentrant. Any asynchronous exception
178 * is a serious error. Loop infinitely.
179 * -----------------------------------------------------
180 */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100181irq_sp_el0:
Soby Mathewc1adbbc2014-06-25 10:07:40 +0100182 bl report_unhandled_interrupt
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000183 check_vector_size irq_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100184
185 .align 7
186fiq_sp_el0:
Soby Mathewc1adbbc2014-06-25 10:07:40 +0100187 bl report_unhandled_interrupt
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000188 check_vector_size fiq_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100189
190 .align 7
191serror_sp_el0:
Soby Mathewc1adbbc2014-06-25 10:07:40 +0100192 bl report_unhandled_exception
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000193 check_vector_size serror_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100194
195 /* -----------------------------------------------------
196 * Current EL with SPx: 0x200 - 0x380
197 * -----------------------------------------------------
198 */
199 .align 7
200sync_exception_sp_elx:
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000201 /* -----------------------------------------------------
202 * This exception will trigger if anything went wrong
203 * during a previous exception entry or exit or while
204 * handling an earlier unexpected synchronous exception.
Soby Mathew5e5c2072014-04-07 15:28:55 +0100205 * There is a high probability that SP_EL3 is corrupted.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000206 * -----------------------------------------------------
207 */
Soby Mathewc1adbbc2014-06-25 10:07:40 +0100208 bl report_unhandled_exception
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000209 check_vector_size sync_exception_sp_elx
Achin Gupta4f6ad662013-10-25 09:08:21 +0100210
211 .align 7
212irq_sp_elx:
Soby Mathewc1adbbc2014-06-25 10:07:40 +0100213 bl report_unhandled_interrupt
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000214 check_vector_size irq_sp_elx
215
Achin Gupta4f6ad662013-10-25 09:08:21 +0100216 .align 7
217fiq_sp_elx:
Soby Mathewc1adbbc2014-06-25 10:07:40 +0100218 bl report_unhandled_interrupt
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000219 check_vector_size fiq_sp_elx
220
Achin Gupta4f6ad662013-10-25 09:08:21 +0100221 .align 7
222serror_sp_elx:
Soby Mathewc1adbbc2014-06-25 10:07:40 +0100223 bl report_unhandled_exception
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000224 check_vector_size serror_sp_elx
Achin Gupta4f6ad662013-10-25 09:08:21 +0100225
226 /* -----------------------------------------------------
227 * Lower EL using AArch64 : 0x400 - 0x580
228 * -----------------------------------------------------
229 */
230 .align 7
231sync_exception_aarch64:
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000232 /* -----------------------------------------------------
233 * This exception vector will be the entry point for
234 * SMCs and traps that are unhandled at lower ELs most
235 * commonly. SP_EL3 should point to a valid cpu context
236 * where the general purpose and system register state
237 * can be saved.
238 * -----------------------------------------------------
239 */
240 handle_sync_exception
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000241 check_vector_size sync_exception_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100242
243 .align 7
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000244 /* -----------------------------------------------------
245 * Asynchronous exceptions from lower ELs are not
246 * currently supported. Report their occurrence.
247 * -----------------------------------------------------
248 */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100249irq_aarch64:
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100250 handle_interrupt_exception irq_aarch64
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000251 check_vector_size irq_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100252
253 .align 7
254fiq_aarch64:
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100255 handle_interrupt_exception fiq_aarch64
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000256 check_vector_size fiq_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100257
258 .align 7
259serror_aarch64:
Soby Mathewc1adbbc2014-06-25 10:07:40 +0100260 bl report_unhandled_exception
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000261 check_vector_size serror_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100262
263 /* -----------------------------------------------------
264 * Lower EL using AArch32 : 0x600 - 0x780
265 * -----------------------------------------------------
266 */
267 .align 7
268sync_exception_aarch32:
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000269 /* -----------------------------------------------------
270 * This exception vector will be the entry point for
271 * SMCs and traps that are unhandled at lower ELs most
272 * commonly. SP_EL3 should point to a valid cpu context
273 * where the general purpose and system register state
274 * can be saved.
275 * -----------------------------------------------------
276 */
277 handle_sync_exception
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000278 check_vector_size sync_exception_aarch32
Achin Gupta4f6ad662013-10-25 09:08:21 +0100279
280 .align 7
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000281 /* -----------------------------------------------------
282 * Asynchronous exceptions from lower ELs are not
283 * currently supported. Report their occurrence.
284 * -----------------------------------------------------
285 */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100286irq_aarch32:
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100287 handle_interrupt_exception irq_aarch32
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000288 check_vector_size irq_aarch32
Achin Gupta4f6ad662013-10-25 09:08:21 +0100289
290 .align 7
291fiq_aarch32:
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100292 handle_interrupt_exception fiq_aarch32
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000293 check_vector_size fiq_aarch32
Achin Gupta4f6ad662013-10-25 09:08:21 +0100294
295 .align 7
296serror_aarch32:
Soby Mathewc1adbbc2014-06-25 10:07:40 +0100297 bl report_unhandled_exception
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000298 check_vector_size serror_aarch32
299
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000300 .align 7
301
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000302 /* -----------------------------------------------------
303 * The following code handles secure monitor calls.
304 * Depending upon the execution state from where the SMC
305 * has been invoked, it frees some general purpose
306 * registers to perform the remaining tasks. They
307 * involve finding the runtime service handler that is
308 * the target of the SMC & switching to runtime stacks
309 * (SP_EL0) before calling the handler.
310 *
311 * Note that x30 has been explicitly saved and can be
312 * used here
313 * -----------------------------------------------------
314 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000315func smc_handler
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000316smc_handler32:
317 /* Check whether aarch32 issued an SMC64 */
318 tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited
319
320 /* -----------------------------------------------------
321 * Since we're are coming from aarch32, x8-x18 need to
322 * be saved as per SMC32 calling convention. If a lower
323 * EL in aarch64 is making an SMC32 call then it must
324 * have saved x8-x17 already therein.
325 * -----------------------------------------------------
326 */
327 stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
328 stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10]
329 stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12]
330 stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14]
331 stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
332
333 /* x4-x7, x18, sp_el0 are saved below */
334
335smc_handler64:
336 /* -----------------------------------------------------
337 * Populate the parameters for the SMC handler. We
338 * already have x0-x4 in place. x5 will point to a
339 * cookie (not used now). x6 will point to the context
340 * structure (SP_EL3) and x7 will contain flags we need
341 * to pass to the handler Hence save x5-x7. Note that x4
342 * only needs to be preserved for AArch32 callers but we
343 * do it for AArch64 callers as well for convenience
344 * -----------------------------------------------------
345 */
346 stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
347 stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
348
Soby Mathew6c5192a2014-04-30 15:36:37 +0100349 /* Save rest of the gpregs and sp_el0*/
350 save_x18_to_x29_sp_el0
351
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000352 mov x5, xzr
353 mov x6, sp
354
355 /* Get the unique owning entity number */
356 ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH
357 ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH
358 orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH
359
360 adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE)
361
362 /* Load descriptor index from array of indices */
363 adr x14, rt_svc_descs_indices
364 ldrb w15, [x14, x16]
365
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000366 /* -----------------------------------------------------
367 * Restore the saved C runtime stack value which will
368 * become the new SP_EL0 i.e. EL3 runtime stack. It was
369 * saved in the 'cpu_context' structure prior to the last
370 * ERET from EL3.
371 * -----------------------------------------------------
372 */
373 ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
374
375 /*
376 * Any index greater than 127 is invalid. Check bit 7 for
377 * a valid index
378 */
379 tbnz w15, 7, smc_unknown
380
381 /* Switch to SP_EL0 */
382 msr spsel, #0
383
384 /* -----------------------------------------------------
385 * Get the descriptor using the index
386 * x11 = (base + off), x15 = index
387 *
388 * handler = (base + off) + (index << log2(size))
389 * -----------------------------------------------------
390 */
391 lsl w10, w15, #RT_SVC_SIZE_LOG2
392 ldr x15, [x11, w10, uxtw]
393
394 /* -----------------------------------------------------
395 * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there
396 * is a world switch during SMC handling.
397 * TODO: Revisit if all system registers can be saved
398 * later.
399 * -----------------------------------------------------
400 */
401 mrs x16, spsr_el3
402 mrs x17, elr_el3
403 mrs x18, scr_el3
404 stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
Achin Guptae1aa5162014-06-26 09:58:52 +0100405 str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000406
407 /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */
408 bfi x7, x18, #0, #1
409
410 mov sp, x12
411
412 /* -----------------------------------------------------
413 * Call the Secure Monitor Call handler and then drop
414 * directly into el3_exit() which will program any
415 * remaining architectural state prior to issuing the
416 * ERET to the desired lower EL.
417 * -----------------------------------------------------
418 */
419#if DEBUG
420 cbz x15, rt_svc_fw_critical_error
421#endif
422 blr x15
423
424 /* -----------------------------------------------------
425 * This routine assumes that the SP_EL3 is pointing to
426 * a valid context structure from where the gp regs and
427 * other special registers can be retrieved.
Andrew Thoelke38bde412014-03-18 13:46:55 +0000428 *
429 * Keep it in the same section as smc_handler as this
430 * function uses a fall-through to el3_exit
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000431 * -----------------------------------------------------
432 */
433el3_exit: ; .type el3_exit, %function
434 /* -----------------------------------------------------
435 * Save the current SP_EL0 i.e. the EL3 runtime stack
436 * which will be used for handling the next SMC. Then
437 * switch to SP_EL3
438 * -----------------------------------------------------
439 */
440 mov x17, sp
441 msr spsel, #1
442 str x17, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
443
444 /* -----------------------------------------------------
445 * Restore SPSR_EL3, ELR_EL3 and SCR_EL3 prior to ERET
446 * -----------------------------------------------------
447 */
Achin Guptae1aa5162014-06-26 09:58:52 +0100448 ldr x18, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000449 ldp x16, x17, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
450 msr scr_el3, x18
451 msr spsr_el3, x16
452 msr elr_el3, x17
453
454 /* Restore saved general purpose registers and return */
Soby Mathew5e5c2072014-04-07 15:28:55 +0100455 b restore_gp_registers_eret
Achin Gupta4f6ad662013-10-25 09:08:21 +0100456
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000457smc_unknown:
458 /*
459 * Here we restore x4-x18 regardless of where we came from. AArch32
460 * callers will find the registers contents unchanged, but AArch64
461 * callers will find the registers modified (with stale earlier NS
462 * content). Either way, we aren't leaking any secure information
463 * through them
464 */
Soby Mathew5e5c2072014-04-07 15:28:55 +0100465 mov w0, #SMC_UNK
466 b restore_gp_registers_callee_eret
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000467
468smc_prohibited:
Soby Mathew6c5192a2014-04-30 15:36:37 +0100469 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000470 mov w0, #SMC_UNK
471 eret
472
473rt_svc_fw_critical_error:
Soby Mathew5e5c2072014-04-07 15:28:55 +0100474 msr spsel, #1 /* Switch to SP_ELx */
Soby Mathewc1adbbc2014-06-25 10:07:40 +0100475 bl report_unhandled_exception
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000476
477 /* -----------------------------------------------------
478 * The following functions are used to saved and restore
Soby Mathew6c5192a2014-04-30 15:36:37 +0100479 * all the general pupose registers. Ideally we would
480 * only save and restore the callee saved registers when
481 * a world switch occurs but that type of implementation
482 * is more complex. So currently we will always save and
483 * restore these registers on entry and exit of EL3.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000484 * These are not macros to ensure their invocation fits
485 * within the 32 instructions per exception vector.
486 * -----------------------------------------------------
487 */
Soby Mathew6c5192a2014-04-30 15:36:37 +0100488func save_gp_registers
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000489 stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
490 stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
491 stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
492 stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
493 stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
494 stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10]
495 stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12]
496 stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14]
497 stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
Soby Mathew6c5192a2014-04-30 15:36:37 +0100498 save_x18_to_x29_sp_el0
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000499 ret
500
Soby Mathew5e5c2072014-04-07 15:28:55 +0100501func restore_gp_registers_eret
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000502 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
503 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
504
Soby Mathew5e5c2072014-04-07 15:28:55 +0100505restore_gp_registers_callee_eret:
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000506 ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
507 ldp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
508 ldp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
509 ldp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10]
510 ldp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12]
511 ldp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14]
Soby Mathew6c5192a2014-04-30 15:36:37 +0100512 ldp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18]
513 ldp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20]
514 ldp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22]
515 ldp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24]
516 ldp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26]
517 ldp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
Soby Mathew5e5c2072014-04-07 15:28:55 +0100518 ldp x30, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
519 msr sp_el0, x17
520 ldp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
521 eret