| developer | 65014b8 | 2015-04-13 14:47:57 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | #ifndef __UART8250_H__ |
| 31 | #define __UART8250_H__ |
| 32 | |
| 33 | /* UART register */ |
| 34 | #define UART_RBR 0x00 /* Receive buffer register */ |
| 35 | #define UART_DLL 0x00 /* Divisor latch lsb */ |
| 36 | #define UART_THR 0x00 /* Transmit holding register */ |
| 37 | #define UART_DLH 0x04 /* Divisor latch msb */ |
| 38 | #define UART_IER 0x04 /* Interrupt enable register */ |
| 39 | #define UART_FCR 0x08 /* FIFO control register */ |
| 40 | #define UART_LCR 0x0c /* Line control register */ |
| 41 | #define UART_MCR 0x10 /* Modem control register */ |
| 42 | #define UART_LSR 0x14 /* Line status register */ |
| 43 | #define UART_HIGHSPEED 0x24 /* High speed UART */ |
| 44 | |
| 45 | /* FCR */ |
| 46 | #define UART_FCR_FIFO_EN 0x01 /* enable FIFO */ |
| 47 | #define UART_FCR_CLEAR_RCVR 0x02 /* clear the RCVR FIFO */ |
| 48 | #define UART_FCR_CLEAR_XMIT 0x04 /* clear the XMIT FIFO */ |
| 49 | |
| 50 | /* LCR */ |
| 51 | #define UART_LCR_WLS_8 0x03 /* 8 bit character length */ |
| 52 | #define UART_LCR_DLAB 0x80 /* divisor latch access bit */ |
| 53 | |
| 54 | /* MCR */ |
| 55 | #define UART_MCR_DTR 0x01 |
| 56 | #define UART_MCR_RTS 0x02 |
| 57 | |
| 58 | /* LSR */ |
| 59 | #define UART_LSR_DR 0x01 /* Data ready */ |
| 60 | #define UART_LSR_THRE 0x20 /* Xmit holding register empty */ |
| 61 | |
| 62 | #endif /* __UART8250_H__ */ |