blob: 88954614045d66c274babf5ea7bb8d5da8f3bd71 [file] [log] [blame]
Juan Castillofacdd1c2015-08-12 12:53:02 +01001/*
2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <errno.h>
32#include <mmio.h>
33#include <norflash.h>
34
35/* Helper macros to access two flash banks in parallel */
36#define NOR_2X16(d) ((d << 16) | (d & 0xffff))
37
38/*
39 * DWS ready poll retries. The number of retries in this driver have been
40 * obtained empirically from Juno. FVP implements a zero wait state NOR flash
41 * model
42 */
43#define DWS_WORD_PROGRAM_RETRIES 1000
44
45/*
46 * Poll Write State Machine. Return values:
47 * 0 = WSM ready
48 * -EBUSY = WSM busy after the number of retries
49 */
50static int nor_poll_dws(uintptr_t base_addr, unsigned int retries)
51{
52 uint32_t status;
53 int ret;
54
55 for (;;) {
56 nor_send_cmd(base_addr, NOR_CMD_READ_STATUS_REG);
57 status = mmio_read_32(base_addr);
58 if ((status & NOR_DWS) &&
59 (status & (NOR_DWS << 16))) {
60 ret = 0;
61 break;
62 }
63 if (retries-- == 0) {
64 ret = -EBUSY;
65 break;
66 }
67 }
68
69 return ret;
70}
71
72void nor_send_cmd(uintptr_t base_addr, unsigned long cmd)
73{
74 mmio_write_32(base_addr, NOR_2X16(cmd));
75}
76
77/*
78 * Return values:
79 * 0 = success
80 * -EBUSY = WSM not ready
81 * -EPERM = Device protected or Block locked
82 */
83int nor_word_program(uintptr_t base_addr, unsigned long data)
84{
85 uint32_t status;
86 int ret;
87
88 /* Set the device in write word mode */
89 nor_send_cmd(base_addr, NOR_CMD_WORD_PROGRAM);
90 mmio_write_32(base_addr, data);
91
92 ret = nor_poll_dws(base_addr, DWS_WORD_PROGRAM_RETRIES);
93 if (ret != 0) {
94 goto word_program_end;
95 }
96
97 /* Full status check */
98 nor_send_cmd(base_addr, NOR_CMD_READ_STATUS_REG);
99 status = mmio_read_32(base_addr);
100
101 if (status & (NOR_PS | NOR_BLS)) {
102 nor_send_cmd(base_addr, NOR_CMD_CLEAR_STATUS_REG);
103 ret = -EPERM;
104 }
105
106word_program_end:
107 nor_send_cmd(base_addr, NOR_CMD_READ_ARRAY);
108 return ret;
109}
110
111void nor_lock(uintptr_t base_addr)
112{
113 nor_send_cmd(base_addr, NOR_CMD_LOCK_UNLOCK);
114 mmio_write_32(base_addr, NOR_2X16(NOR_LOCK_BLOCK));
115 nor_send_cmd(base_addr, NOR_CMD_READ_ARRAY);
116}
117
118void nor_unlock(uintptr_t base_addr)
119{
120 nor_send_cmd(base_addr, NOR_CMD_LOCK_UNLOCK);
121 mmio_write_32(base_addr, NOR_2X16(NOR_UNLOCK_BLOCK));
122 nor_send_cmd(base_addr, NOR_CMD_READ_ARRAY);
123}
124