| Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #ifndef __CORTEX_A57_H__ |
| 32 | #define __CORTEX_A57_H__ |
| 33 | |
| 34 | /* Cortex-A57 midr for revision 0 */ |
| 35 | #define CORTEX_A57_MIDR 0x410FD070 |
| 36 | |
| 37 | /* Retention timer tick definitions */ |
| 38 | #define RETENTION_ENTRY_TICKS_2 0x1 |
| 39 | #define RETENTION_ENTRY_TICKS_8 0x2 |
| 40 | #define RETENTION_ENTRY_TICKS_32 0x3 |
| 41 | #define RETENTION_ENTRY_TICKS_64 0x4 |
| 42 | #define RETENTION_ENTRY_TICKS_128 0x5 |
| 43 | #define RETENTION_ENTRY_TICKS_256 0x6 |
| 44 | #define RETENTION_ENTRY_TICKS_512 0x7 |
| 45 | |
| 46 | /******************************************************************************* |
| 47 | * CPU Extended Control register specific definitions. |
| 48 | ******************************************************************************/ |
| 49 | #define CPUECTLR p15, 1, c15 /* Instruction def. */ |
| 50 | |
| 51 | #define CPUECTLR_SMP_BIT (1 << 6) |
| 52 | #define CPUECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38) |
| 53 | #define CPUECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35) |
| 54 | #define CPUECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32) |
| 55 | |
| 56 | #define CPUECTLR_CPU_RET_CTRL_SHIFT 0 |
| 57 | #define CPUECTLR_CPU_RET_CTRL_MASK (0x7 << CPUECTLR_CPU_RET_CTRL_SHIFT) |
| 58 | |
| 59 | /******************************************************************************* |
| 60 | * CPU Memory Error Syndrome register specific definitions. |
| 61 | ******************************************************************************/ |
| 62 | #define CPUMERRSR p15, 2, c15 /* Instruction def. */ |
| 63 | |
| 64 | /******************************************************************************* |
| 65 | * CPU Auxiliary Control register specific definitions. |
| 66 | ******************************************************************************/ |
| 67 | #define CPUACTLR p15, 0, c15 /* Instruction def. */ |
| 68 | |
| 69 | #define CPUACTLR_DIS_LOAD_PASS_DMB (1 << 59) |
| 70 | #define CPUACTLR_GRE_NGRE_AS_NGNRE (1 << 54) |
| 71 | #define CPUACTLR_DIS_OVERREAD (1 << 52) |
| 72 | #define CPUACTLR_NO_ALLOC_WBWA (1 << 49) |
| 73 | #define CPUACTLR_DCC_AS_DCCI (1 << 44) |
| 74 | #define CPUACTLR_FORCE_FPSCR_FLUSH (1 << 38) |
| 75 | #define CPUACTLR_DIS_STREAMING (3 << 27) |
| 76 | #define CPUACTLR_DIS_L1_STREAMING (3 << 25) |
| 77 | #define CPUACTLR_DIS_INDIRECT_PREDICTOR (1 << 4) |
| 78 | |
| 79 | /******************************************************************************* |
| 80 | * L2 Control register specific definitions. |
| 81 | ******************************************************************************/ |
| 82 | #define L2CTLR p15, 1, c9, c0, 3 /* Instruction def. */ |
| 83 | |
| 84 | #define L2CTLR_DATA_RAM_LATENCY_SHIFT 0 |
| 85 | #define L2CTLR_TAG_RAM_LATENCY_SHIFT 6 |
| 86 | |
| 87 | #define L2_DATA_RAM_LATENCY_3_CYCLES 0x2 |
| 88 | #define L2_TAG_RAM_LATENCY_3_CYCLES 0x2 |
| 89 | |
| 90 | /******************************************************************************* |
| 91 | * L2 Extended Control register specific definitions. |
| 92 | ******************************************************************************/ |
| 93 | #define L2ECTLR p15, 1, c9, c0, 3 /* Instruction def. */ |
| 94 | |
| 95 | #define L2ECTLR_RET_CTRL_SHIFT 0 |
| 96 | #define L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT) |
| 97 | |
| 98 | /******************************************************************************* |
| 99 | * L2 Memory Error Syndrome register specific definitions. |
| 100 | ******************************************************************************/ |
| 101 | #define L2MERRSR p15, 3, c15 /* Instruction def. */ |
| 102 | |
| 103 | #endif /* __CORTEX_A57_H__ */ |