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Haojian Zhuang5f281b32017-05-24 08:45:05 +08001/*
Haojian Zhuang3bd94382018-01-28 23:33:02 +08002 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
Haojian Zhuang5f281b32017-05-24 08:45:05 +08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01007#ifndef PLATFORM_DEF_H
8#define PLATFORM_DEF_H
Haojian Zhuang5f281b32017-05-24 08:45:05 +08009
10#include <arch.h>
Michael Brandlafdff3c2018-02-22 16:30:30 +010011#include <common_def.h>
12#include <hikey_def.h>
13#include <hikey_layout.h> /* BL memory region sizes, etc */
14#include <tbbr_img_def.h>
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010015#include <utils_def.h>
Haojian Zhuang5f281b32017-05-24 08:45:05 +080016
Victor Chong2d9a42d2017-08-17 15:21:10 +090017/* Special value used to verify platform parameters from BL2 to BL3-1 */
18#define HIKEY_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
19
Haojian Zhuang5f281b32017-05-24 08:45:05 +080020/*
Haojian Zhuang5f281b32017-05-24 08:45:05 +080021 * Generic platform constants
22 */
23
24/* Size of cacheable stacks */
Teddy Reed349cf892018-06-22 22:23:36 -040025#define PLATFORM_STACK_SIZE 0x1000
Haojian Zhuang5f281b32017-05-24 08:45:05 +080026
27#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
28
29#define PLATFORM_CACHE_LINE_SIZE 64
30#define PLATFORM_CLUSTER_COUNT 2
31#define PLATFORM_CORE_COUNT_PER_CLUSTER 4
32#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
33 PLATFORM_CORE_COUNT_PER_CLUSTER)
Michael Brandlafdff3c2018-02-22 16:30:30 +010034#define PLAT_MAX_PWR_LVL (MPIDR_AFFLVL2)
Haojian Zhuang5f281b32017-05-24 08:45:05 +080035#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
36 PLATFORM_CLUSTER_COUNT + 1)
37
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010038#define PLAT_MAX_RET_STATE U(1)
39#define PLAT_MAX_OFF_STATE U(2)
Haojian Zhuang5f281b32017-05-24 08:45:05 +080040
41#define MAX_IO_DEVICES 3
42#define MAX_IO_HANDLES 4
43/* eMMC RPMB and eMMC User Data */
44#define MAX_IO_BLOCK_DEVICES 2
45
46/* GIC related constants (no GICR in GIC-400) */
47#define PLAT_ARM_GICD_BASE 0xF6801000
48#define PLAT_ARM_GICC_BASE 0xF6802000
49#define PLAT_ARM_GICH_BASE 0xF6804000
50#define PLAT_ARM_GICV_BASE 0xF6806000
51
Haojian Zhuang5f281b32017-05-24 08:45:05 +080052/*
53 * Platform specific page table and MMU setup constants
54 */
Antonio Nino Diaz42c7bbd2018-09-24 17:15:05 +010055#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
56#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
Haojian Zhuang5f281b32017-05-24 08:45:05 +080057
Roberto Vargas82477962017-10-23 08:22:17 +010058#if defined(IMAGE_BL1) || defined(IMAGE_BL32)
Haojian Zhuang5f281b32017-05-24 08:45:05 +080059#define MAX_XLAT_TABLES 3
60#endif
61
Roberto Vargas82477962017-10-23 08:22:17 +010062#ifdef IMAGE_BL31
Victor Chongb9a8db22017-05-28 00:14:25 +090063#define MAX_XLAT_TABLES 4
Victor Chong7d787f52017-08-16 13:53:56 +090064#endif
65
Roberto Vargas82477962017-10-23 08:22:17 +010066#ifdef IMAGE_BL2
Victor Chong7d787f52017-08-16 13:53:56 +090067#define MAX_XLAT_TABLES 4
Victor Chongb9a8db22017-05-28 00:14:25 +090068#endif
69
Haojian Zhuang5f281b32017-05-24 08:45:05 +080070#define MAX_MMAP_REGIONS 16
71
Haojian Zhuang5f281b32017-05-24 08:45:05 +080072/*
73 * Declarations and constants to access the mailboxes safely. Each mailbox is
74 * aligned on the biggest cache line size in the platform. This is known only
75 * to the platform as it might have a combination of integrated and external
76 * caches. Such alignment ensures that two maiboxes do not sit on the same cache
77 * line at any cache level. They could belong to different cpus/clusters &
78 * get written while being protected by different locks causing corruption of
79 * a valid mailbox address.
80 */
81#define CACHE_WRITEBACK_SHIFT 6
82#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
83
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010084#endif /* PLATFORM_DEF_H */