| Pankaj Gupta | 90ae1a0 | 2020-12-09 14:02:41 +0530 | [diff] [blame] | 1 | # |
| 2 | # Copyright 2021 NXP |
| 3 | # |
| 4 | # SPDX-License-Identifier: BSD-3-Clause |
| 5 | # |
| 6 | |
| 7 | # board-specific build parameters |
| 8 | |
| 9 | BOOT_MODE ?= flexspi_nor |
| 10 | BOARD ?= lx2160ardb |
| 11 | POVDD_ENABLE := no |
| 12 | NXP_COINED_BB := no |
| 13 | |
| 14 | # DDR Compilation Configs |
| 15 | NUM_OF_DDRC := 2 |
| 16 | DDRC_NUM_DIMM := 2 |
| 17 | DDRC_NUM_CS := 4 |
| 18 | DDR_ECC_EN := yes |
| 19 | #enable address decoding feature |
| 20 | DDR_ADDR_DEC := yes |
| 21 | APPLY_MAX_CDD := yes |
| 22 | |
| 23 | # DDR Errata |
| 24 | ERRATA_DDR_A011396 := 1 |
| 25 | ERRATA_DDR_A050450 := 1 |
| 26 | |
| 27 | # On-Board Flash Details |
| 28 | FLASH_TYPE := MT35XU512A |
| 29 | XSPI_FLASH_SZ := 0x10000000 |
| 30 | NXP_XSPI_NOR_UNIT_SIZE := 0x20000 |
| 31 | BL2_BIN_XSPI_NOR_END_ADDRESS := 0x100000 |
| 32 | # CONFIG_FSPI_ERASE_4K is required to erase 4K sector sizes. This |
| 33 | # config is enabled for future use cases. |
| 34 | FSPI_ERASE_4K := 0 |
| 35 | |
| 36 | # Platform specific features. |
| 37 | WARM_BOOT := no |
| 38 | |
| 39 | # Adding platform specific defines |
| 40 | |
| 41 | $(eval $(call add_define_val,BOARD,'"${BOARD}"')) |
| 42 | |
| 43 | ifeq (${POVDD_ENABLE},yes) |
| 44 | $(eval $(call add_define,CONFIG_POVDD_ENABLE)) |
| 45 | endif |
| 46 | |
| 47 | ifneq (${FLASH_TYPE},) |
| 48 | $(eval $(call add_define,CONFIG_${FLASH_TYPE})) |
| 49 | endif |
| 50 | |
| 51 | ifneq (${XSPI_FLASH_SZ},) |
| 52 | $(eval $(call add_define_val,NXP_FLEXSPI_FLASH_SIZE,${XSPI_FLASH_SZ})) |
| 53 | endif |
| 54 | |
| 55 | ifneq (${FSPI_ERASE_4K},) |
| 56 | $(eval $(call add_define_val,CONFIG_FSPI_ERASE_4K,${FSPI_ERASE_4K})) |
| 57 | endif |
| 58 | |
| 59 | ifneq (${NUM_OF_DDRC},) |
| 60 | $(eval $(call add_define_val,NUM_OF_DDRC,${NUM_OF_DDRC})) |
| 61 | endif |
| 62 | |
| 63 | ifneq (${DDRC_NUM_DIMM},) |
| 64 | $(eval $(call add_define_val,DDRC_NUM_DIMM,${DDRC_NUM_DIMM})) |
| 65 | endif |
| 66 | |
| 67 | ifneq (${DDRC_NUM_CS},) |
| 68 | $(eval $(call add_define_val,DDRC_NUM_CS,${DDRC_NUM_CS})) |
| 69 | endif |
| 70 | |
| 71 | ifeq (${DDR_ADDR_DEC},yes) |
| 72 | $(eval $(call add_define,CONFIG_DDR_ADDR_DEC)) |
| 73 | endif |
| 74 | |
| 75 | ifeq (${DDR_ECC_EN},yes) |
| 76 | $(eval $(call add_define,CONFIG_DDR_ECC_EN)) |
| 77 | endif |
| 78 | |
| 79 | # Platform can control the base address for non-volatile storage. |
| 80 | #$(eval $(call add_define_val,NV_STORAGE_BASE_ADDR,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - 2 * ${NXP_XSPI_NOR_UNIT_SIZE}')) |
| 81 | |
| 82 | ifeq (${WARM_BOOT},yes) |
| 83 | $(eval $(call add_define_val,PHY_TRAINING_REGS_ON_FLASH,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - ${NXP_XSPI_NOR_UNIT_SIZE}')) |
| 84 | endif |
| 85 | |
| 86 | # Adding Platform files build files |
| 87 | BL2_SOURCES += ${BOARD_PATH}/ddr_init.c\ |
| 88 | ${BOARD_PATH}/platform.c |
| 89 | |
| 90 | # Adding SoC build info |
| 91 | include plat/nxp/soc-lx2160a/soc.mk |