| developer | 5f73516 | 2021-01-04 00:02:34 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2020, MediaTek Inc. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <stddef.h> |
| 8 | #include <string.h> |
| 9 | #include <common/debug.h> |
| 10 | #include <lib/bakery_lock.h> |
| 11 | #include <lib/mmio.h> |
| 12 | #include <mt_lp_rm.h> |
| 13 | #include <mt_spm.h> |
| 14 | #include <mt_spm_cond.h> |
| 15 | #include <mt_spm_conservation.h> |
| 16 | #include <mt_spm_constraint.h> |
| 17 | #include <mt_spm_idle.h> |
| 18 | #include <mt_spm_internal.h> |
| 19 | #include <mt_spm_pmic_wrap.h> |
| 20 | #include <mt_spm_rc_internal.h> |
| 21 | #include <mt_spm_reg.h> |
| 22 | #include <mt_spm_resource_req.h> |
| 23 | #include <mt_spm_suspend.h> |
| 24 | #include <mtk_plat_common.h> |
| 25 | #include <plat_mtk_lpm.h> |
| 26 | #include <plat_pm.h> |
| 27 | #include <platform_def.h> |
| 28 | #include <sleep_def.h> |
| 29 | |
| 30 | #ifdef MT_SPM_USING_BAKERY_LOCK |
| 31 | DEFINE_BAKERY_LOCK(spm_lock); |
| 32 | #define plat_spm_lock_init() bakery_lock_init(&spm_lock) |
| 33 | #else |
| 34 | spinlock_t spm_lock; |
| 35 | #define plat_spm_lock_init() |
| 36 | #endif |
| 37 | |
| 38 | /* CLK_SCP_CFG_0 */ |
| 39 | #define CLK_SCP_CFG_0 (TOPCKGEN_BASE + 0x200) |
| 40 | #define SPM_CK_CONTROL_EN 0x3FF |
| 41 | |
| 42 | /* CLK_SCP_CFG_1 */ |
| 43 | #define CLK_SCP_CFG_1 (TOPCKGEN_BASE + 0x210) |
| 44 | #define CLK_SCP_CFG_1_MASK 0x100C |
| 45 | #define CLK_SCP_CFG_1_SPM 0x3 |
| 46 | |
| 47 | struct mt_resource_constraint plat_constraint_bus26m = { |
| 48 | .is_valid = spm_is_valid_rc_bus26m, |
| 49 | .update = spm_update_rc_bus26m, |
| 50 | .allow = spm_allow_rc_bus26m, |
| 51 | .run = spm_run_rc_bus26m, |
| 52 | .reset = spm_reset_rc_bus26m, |
| 53 | }; |
| 54 | |
| 55 | struct mt_resource_constraint plat_constraint_syspll = { |
| 56 | .is_valid = spm_is_valid_rc_syspll, |
| 57 | .update = spm_update_rc_syspll, |
| 58 | .allow = spm_allow_rc_syspll, |
| 59 | .run = spm_run_rc_syspll, |
| 60 | .reset = spm_reset_rc_syspll, |
| 61 | }; |
| 62 | |
| 63 | struct mt_resource_constraint plat_constraint_dram = { |
| 64 | .is_valid = spm_is_valid_rc_dram, |
| 65 | .update = spm_update_rc_dram, |
| 66 | .allow = spm_allow_rc_dram, |
| 67 | .run = spm_run_rc_dram, |
| 68 | .reset = spm_reset_rc_dram, |
| 69 | }; |
| 70 | |
| 71 | struct mt_resource_constraint plat_constraint_cpu = { |
| 72 | .is_valid = spm_is_valid_rc_cpu_buck_ldo, |
| 73 | .update = NULL, |
| 74 | .allow = spm_allow_rc_cpu_buck_ldo, |
| 75 | .run = spm_run_rc_cpu_buck_ldo, |
| 76 | .reset = spm_reset_rc_cpu_buck_ldo, |
| 77 | }; |
| 78 | |
| 79 | struct mt_resource_constraint *plat_constraints[] = { |
| 80 | &plat_constraint_bus26m, |
| 81 | &plat_constraint_syspll, |
| 82 | &plat_constraint_dram, |
| 83 | &plat_constraint_cpu, |
| 84 | NULL, |
| 85 | }; |
| 86 | |
| 87 | struct mt_resource_manager plat_mt8192_rm = { |
| 88 | .update = mt_spm_cond_update, |
| 89 | .consts = plat_constraints, |
| 90 | }; |
| 91 | |
| 92 | void spm_boot_init(void) |
| 93 | { |
| 94 | /* switch ck_off/axi_26m control to SPM */ |
| 95 | mmio_setbits_32(CLK_SCP_CFG_0, SPM_CK_CONTROL_EN); |
| 96 | mmio_clrsetbits_32(CLK_SCP_CFG_1, CLK_SCP_CFG_1_MASK, |
| 97 | CLK_SCP_CFG_1_SPM); |
| 98 | |
| 99 | plat_spm_lock_init(); |
| 100 | mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE); |
| 101 | mt_lp_rm_register(&plat_mt8192_rm); |
| 102 | mt_spm_idle_generic_init(); |
| 103 | mt_spm_suspend_init(); |
| 104 | } |