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git01.mediatek.com / filogic / atf / c883ce045b3529d7c5ff7de8f7dc376ddee4bd58 / . / plat / qti / common / src / qti_gic_v3.c
blob: f00267acdd36089712e8d74ea62061dd7edc8cd5 [file] [log] [blame]
Saurabh Gorecha70389ca2020-04-22 21:31:24 +0530[diff] [blame]1/*
2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Saurabh Gorecha43987c52021-05-24 17:35:34 +0530[diff] [blame]3 * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
Saurabh Gorecha70389ca2020-04-22 21:31:24 +0530[diff] [blame]4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include <common/bl_common.h>
9#include <drivers/arm/gicv3.h>
10
11#include <platform.h>
12#include <platform_def.h>
13#include <qti_plat.h>
14#include <qtiseclib_defs.h>
15#include <qtiseclib_defs_plat.h>
16
17/* The GICv3 driver only needs to be initialized in EL3 */
18static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
19
20/* Array of interrupts to be configured by the gic driver */
21static const interrupt_prop_t qti_interrupt_props[] = {
22 INTR_PROP_DESC(QTISECLIB_INT_ID_CPU_WAKEUP_SGI,
23 GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
24 GIC_INTR_CFG_EDGE),
25 INTR_PROP_DESC(QTISECLIB_INT_ID_RESET_SGI, GIC_HIGHEST_SEC_PRIORITY,
26 INTR_GROUP0,
27 GIC_INTR_CFG_EDGE),
28 INTR_PROP_DESC(QTISECLIB_INT_ID_SEC_WDOG_BARK, GIC_HIGHEST_SEC_PRIORITY,
29 INTR_GROUP0,
30 GIC_INTR_CFG_EDGE),
31 INTR_PROP_DESC(QTISECLIB_INT_ID_NON_SEC_WDOG_BITE,
32 GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
33 GIC_INTR_CFG_LEVEL),
34 INTR_PROP_DESC(QTISECLIB_INT_ID_VMIDMT_ERR_CLT_SEC,
35 GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
36 GIC_INTR_CFG_EDGE),
37 INTR_PROP_DESC(QTISECLIB_INT_ID_VMIDMT_ERR_CLT_NONSEC,
38 GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
39 GIC_INTR_CFG_EDGE),
40 INTR_PROP_DESC(QTISECLIB_INT_ID_VMIDMT_ERR_CFG_SEC,
41 GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
42 GIC_INTR_CFG_EDGE),
43 INTR_PROP_DESC(QTISECLIB_INT_ID_VMIDMT_ERR_CFG_NONSEC,
44 GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
45 GIC_INTR_CFG_EDGE),
46 INTR_PROP_DESC(QTISECLIB_INT_ID_XPU_SEC, GIC_HIGHEST_SEC_PRIORITY,
47 INTR_GROUP0,
48 GIC_INTR_CFG_EDGE),
49 INTR_PROP_DESC(QTISECLIB_INT_ID_XPU_NON_SEC, GIC_HIGHEST_SEC_PRIORITY,
50 INTR_GROUP0,
51 GIC_INTR_CFG_EDGE),
52#ifdef QTISECLIB_INT_ID_A1_NOC_ERROR
53 INTR_PROP_DESC(QTISECLIB_INT_ID_A1_NOC_ERROR, GIC_HIGHEST_SEC_PRIORITY,
54 INTR_GROUP0,
55 GIC_INTR_CFG_EDGE),
56#endif
57 INTR_PROP_DESC(QTISECLIB_INT_ID_A2_NOC_ERROR, GIC_HIGHEST_SEC_PRIORITY,
58 INTR_GROUP0,
59 GIC_INTR_CFG_EDGE),
60 INTR_PROP_DESC(QTISECLIB_INT_ID_CONFIG_NOC_ERROR,
61 GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
62 GIC_INTR_CFG_EDGE),
63 INTR_PROP_DESC(QTISECLIB_INT_ID_DC_NOC_ERROR, GIC_HIGHEST_SEC_PRIORITY,
64 INTR_GROUP0,
65 GIC_INTR_CFG_EDGE),
66 INTR_PROP_DESC(QTISECLIB_INT_ID_MEM_NOC_ERROR, GIC_HIGHEST_SEC_PRIORITY,
67 INTR_GROUP0,
68 GIC_INTR_CFG_EDGE),
69 INTR_PROP_DESC(QTISECLIB_INT_ID_SYSTEM_NOC_ERROR,
70 GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
71 GIC_INTR_CFG_EDGE),
72 INTR_PROP_DESC(QTISECLIB_INT_ID_MMSS_NOC_ERROR,
73 GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
74 GIC_INTR_CFG_EDGE),
Saurabh Gorecha43987c52021-05-24 17:35:34 +0530[diff] [blame]75#ifdef QTISECLIB_INT_ID_LPASS_AGNOC_ERROR
76 INTR_PROP_DESC(QTISECLIB_INT_ID_LPASS_AGNOC_ERROR, GIC_HIGHEST_SEC_PRIORITY,
77 INTR_GROUP0,
78 GIC_INTR_CFG_EDGE),
79#endif
80#ifdef QTISECLIB_INT_ID_NSP_NOC_ERROR
81 INTR_PROP_DESC(QTISECLIB_INT_ID_NSP_NOC_ERROR, GIC_HIGHEST_SEC_PRIORITY,
82 INTR_GROUP0,
83 GIC_INTR_CFG_EDGE),
84#endif
Saurabh Gorecha70389ca2020-04-22 21:31:24 +0530[diff] [blame]85};
86
87const gicv3_driver_data_t qti_gic_data = {
88 .gicd_base = QTI_GICD_BASE,
89 .gicr_base = QTI_GICR_BASE,
90 .interrupt_props = qti_interrupt_props,
91 .interrupt_props_num = ARRAY_SIZE(qti_interrupt_props),
92 .rdistif_num = PLATFORM_CORE_COUNT,
93 .rdistif_base_addrs = rdistif_base_addrs,
94 .mpidr_to_core_pos = plat_qti_core_pos_by_mpidr
95};
96
97void plat_qti_gic_driver_init(void)
98{
99 /*
100 * The GICv3 driver is initialized in EL3 and does not need
101 * to be initialized again in SEL1. This is because the S-EL1
102 * can use GIC system registers to manage interrupts and does
103 * not need GIC interface base addresses to be configured.
104 */
105 gicv3_driver_init(&qti_gic_data);
106}
107
108/******************************************************************************
109 * ARM common helper to initialize the GIC. Only invoked by BL31
110 *****************************************************************************/
111void plat_qti_gic_init(void)
112{
113 unsigned int i;
114
115 gicv3_distif_init();
116 gicv3_rdistif_init(plat_my_core_pos());
117 gicv3_cpuif_enable(plat_my_core_pos());
118
119 /* Route secure spi interrupt to ANY. */
120 for (i = 0; i < ARRAY_SIZE(qti_interrupt_props); i++) {
121 unsigned int int_id = qti_interrupt_props[i].intr_num;
122
123 if (plat_ic_is_spi(int_id)) {
124 gicv3_set_spi_routing(int_id, GICV3_IRM_ANY, 0x0);
125 }
126 }
127}
128
129void gic_set_spi_routing(unsigned int id, unsigned int irm, u_register_t target)
130{
131 gicv3_set_spi_routing(id, irm, target);
132}
133
134/******************************************************************************
135 * ARM common helper to enable the GIC CPU interface
136 *****************************************************************************/
137void plat_qti_gic_cpuif_enable(void)
138{
139 gicv3_cpuif_enable(plat_my_core_pos());
140}
141
142/******************************************************************************
143 * ARM common helper to disable the GIC CPU interface
144 *****************************************************************************/
145void plat_qti_gic_cpuif_disable(void)
146{
147 gicv3_cpuif_disable(plat_my_core_pos());
148}
149
150/******************************************************************************
151 * ARM common helper to initialize the per-CPU redistributor interface in GICv3
152 *****************************************************************************/
153void plat_qti_gic_pcpu_init(void)
154{
155 gicv3_rdistif_init(plat_my_core_pos());
156}
157
158/******************************************************************************
159 * ARM common helpers to power GIC redistributor interface
160 *****************************************************************************/
161void plat_qti_gic_redistif_on(void)
162{
163 gicv3_rdistif_on(plat_my_core_pos());
164}
165
166void plat_qti_gic_redistif_off(void)
167{
168 gicv3_rdistif_off(plat_my_core_pos());
169}