| Robert Marko | 9c523ec | 2021-10-11 16:25:49 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2021 Sartura Ltd. |
| 3 | * Copyright (C) 2021 Globalscale technologies, Inc. |
| 4 | * Copyright (C) 2021 Marvell International Ltd. |
| 5 | * |
| 6 | * SPDX-License-Identifier: BSD-3-Clause |
| 7 | * https://spdx.org/licenses |
| 8 | */ |
| 9 | |
| 10 | #ifndef __PHY_PORTING_LAYER_H |
| 11 | #define __PHY_PORTING_LAYER_H |
| 12 | |
| 13 | #define MAX_LANE_NR 6 |
| 14 | |
| 15 | static const struct xfi_params |
| 16 | xfi_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = { |
| 17 | /* AP0 */ |
| 18 | { |
| 19 | /* CP 0 */ |
| 20 | { |
| 21 | { 0 }, /* Comphy0 */ |
| 22 | { 0 }, /* Comphy1 */ |
| 23 | { 0 }, /* Comphy2 */ |
| 24 | { 0 }, /* Comphy3 */ |
| 25 | { .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf, .align90 = 0x60, |
| 26 | .g1_dfe_res = 0x1, .g1_amp = 0x1c, .g1_emph = 0xe, |
| 27 | .g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1, .g1_tx_emph_en = 0x1, |
| 28 | .g1_tx_emph = 0x0, .g1_rx_selmuff = 0x1, .g1_rx_selmufi = 0x0, |
| 29 | .g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2, |
| 30 | .valid = 1 }, /* Comphy4 */ |
| 31 | { 0 }, /* Comphy5 */ |
| 32 | }, |
| 33 | }, |
| 34 | }; |
| 35 | |
| 36 | static const struct sata_params |
| 37 | sata_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = { |
| 38 | /* AP0 */ |
| 39 | { |
| 40 | /* CP 0 */ |
| 41 | { |
| 42 | { 0 }, /* Comphy0 */ |
| 43 | { 0 }, /* Comphy1 */ |
| 44 | { .g1_amp = 0x8, .g2_amp = 0xa, .g3_amp = 0x1e, |
| 45 | .g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0xe, |
| 46 | .g1_emph_en = 0x1, .g2_emph_en = 0x1, .g3_emph_en = 0x1, |
| 47 | .g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1, .g3_tx_amp_adj = 0x1, |
| 48 | .g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0, .g3_tx_emph_en = 0x0, |
| 49 | .g1_tx_emph = 0x1, .g2_tx_emph = 0x1, .g3_tx_emph = 0x1, |
| 50 | .g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4, .g3_ffe_cap_sel = 0xf, |
| 51 | .align90 = 0x61, |
| 52 | .g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3, .g3_rx_selmuff = 0x3, |
| 53 | .g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0, .g3_rx_selmufi = 0x3, |
| 54 | .g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1, .g3_rx_selmupf = 0x2, |
| 55 | .g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0, .g3_rx_selmupi = 0x2, |
| 56 | .polarity_invert = COMPHY_POLARITY_NO_INVERT, |
| 57 | .valid = 0x1 |
| 58 | }, /* Comphy2 */ |
| 59 | { .g1_amp = 0x8, .g2_amp = 0xa, .g3_amp = 0x1e, |
| 60 | .g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0xe, |
| 61 | .g1_emph_en = 0x1, .g2_emph_en = 0x1, .g3_emph_en = 0x1, |
| 62 | .g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1, .g3_tx_amp_adj = 0x1, |
| 63 | .g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0, .g3_tx_emph_en = 0x0, |
| 64 | .g1_tx_emph = 0x1, .g2_tx_emph = 0x1, .g3_tx_emph = 0x1, |
| 65 | .g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4, .g3_ffe_cap_sel = 0xf, |
| 66 | .align90 = 0x61, |
| 67 | .g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3, .g3_rx_selmuff = 0x3, |
| 68 | .g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0, .g3_rx_selmufi = 0x3, |
| 69 | .g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1, .g3_rx_selmupf = 0x2, |
| 70 | .g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0, .g3_rx_selmupi = 0x2, |
| 71 | .polarity_invert = COMPHY_POLARITY_NO_INVERT, |
| 72 | .valid = 0x1 |
| 73 | }, /* Comphy3 */ |
| 74 | { 0 }, /* Comphy4 */ |
| 75 | { 0 }, /* Comphy5 */ |
| 76 | }, |
| 77 | }, |
| 78 | }; |
| 79 | |
| 80 | static const struct usb_params |
| 81 | usb_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = { |
| 82 | [0 ... AP_NUM-1][0 ... CP_NUM-1][0 ... MAX_LANE_NR-1] = { |
| 83 | .polarity_invert = COMPHY_POLARITY_NO_INVERT |
| 84 | }, |
| 85 | }; |
| 86 | |
| 87 | #endif /* __PHY_PORTING_LAYER_H */ |