laurenw-arm | 7c7b198 | 2020-10-21 13:34:40 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef FVP_R_DEF_H |
| 8 | #define FVP_R_DEF_H |
| 9 | |
| 10 | #include <lib/utils_def.h> |
| 11 | |
johpow01 | 0033b25 | 2021-10-11 14:51:11 -0500 | [diff] [blame] | 12 | /****************************************************************************** |
| 13 | * FVP-R topology constants |
| 14 | *****************************************************************************/ |
| 15 | #define FVP_R_CLUSTER_COUNT 2 |
| 16 | #define FVP_R_MAX_CPUS_PER_CLUSTER 4 |
| 17 | #define FVP_R_MAX_PE_PER_CPU 1 |
| 18 | #define FVP_R_PRIMARY_CPU 0x0 |
laurenw-arm | 7c7b198 | 2020-10-21 13:34:40 -0500 | [diff] [blame] | 19 | |
| 20 | /****************************************************************************** |
| 21 | * Definition of platform soc id |
| 22 | *****************************************************************************/ |
johpow01 | 0033b25 | 2021-10-11 14:51:11 -0500 | [diff] [blame] | 23 | #define FVP_R_SOC_ID 0 |
laurenw-arm | 7c7b198 | 2020-10-21 13:34:40 -0500 | [diff] [blame] | 24 | |
| 25 | /******************************************************************************* |
| 26 | * FVP_R memory map related constants |
| 27 | ******************************************************************************/ |
| 28 | |
Gary Morrison | 3d7f654 | 2021-01-27 13:08:47 -0600 | [diff] [blame] | 29 | #define FLASH1_BASE UL(0x8c000000) |
laurenw-arm | 7c7b198 | 2020-10-21 13:34:40 -0500 | [diff] [blame] | 30 | #define FLASH1_SIZE UL(0x04000000) |
| 31 | |
Gary Morrison | 3d7f654 | 2021-01-27 13:08:47 -0600 | [diff] [blame] | 32 | #define PSRAM_BASE UL(0x94000000) |
laurenw-arm | 7c7b198 | 2020-10-21 13:34:40 -0500 | [diff] [blame] | 33 | #define PSRAM_SIZE UL(0x04000000) |
| 34 | |
Gary Morrison | 3d7f654 | 2021-01-27 13:08:47 -0600 | [diff] [blame] | 35 | #define VRAM_BASE UL(0x98000000) |
laurenw-arm | 7c7b198 | 2020-10-21 13:34:40 -0500 | [diff] [blame] | 36 | #define VRAM_SIZE UL(0x02000000) |
| 37 | |
| 38 | /* Aggregate of all devices in the first GB */ |
Gary Morrison | 3d7f654 | 2021-01-27 13:08:47 -0600 | [diff] [blame] | 39 | #define DEVICE0_BASE UL(0xa0000000) |
laurenw-arm | 7c7b198 | 2020-10-21 13:34:40 -0500 | [diff] [blame] | 40 | #define DEVICE0_SIZE UL(0x0c200000) |
| 41 | |
| 42 | /* |
| 43 | * In case of FVP_R models with CCN, the CCN register space overlaps into |
| 44 | * the NSRAM area. |
| 45 | */ |
Gary Morrison | 3d7f654 | 2021-01-27 13:08:47 -0600 | [diff] [blame] | 46 | #define DEVICE1_BASE UL(0xae000000) |
laurenw-arm | 7c7b198 | 2020-10-21 13:34:40 -0500 | [diff] [blame] | 47 | #define DEVICE1_SIZE UL(0x1A00000) |
Gary Morrison | 3d7f654 | 2021-01-27 13:08:47 -0600 | [diff] [blame] | 48 | |
| 49 | #define NSRAM_BASE UL(0xae000000) |
laurenw-arm | 7c7b198 | 2020-10-21 13:34:40 -0500 | [diff] [blame] | 50 | #define NSRAM_SIZE UL(0x10000) |
| 51 | /* Devices in the second GB */ |
Gary Morrison | 3d7f654 | 2021-01-27 13:08:47 -0600 | [diff] [blame] | 52 | #define DEVICE2_BASE UL(0xffe00000) |
laurenw-arm | 7c7b198 | 2020-10-21 13:34:40 -0500 | [diff] [blame] | 53 | #define DEVICE2_SIZE UL(0x00200000) |
| 54 | |
Gary Morrison | 3d7f654 | 2021-01-27 13:08:47 -0600 | [diff] [blame] | 55 | #define PCIE_EXP_BASE UL(0xc0000000) |
| 56 | #define TZRNG_BASE UL(0x7fe60000) |
| 57 | |
laurenw-arm | 7c7b198 | 2020-10-21 13:34:40 -0500 | [diff] [blame] | 58 | /* Non-volatile counters */ |
Gary Morrison | 3d7f654 | 2021-01-27 13:08:47 -0600 | [diff] [blame] | 59 | #define TRUSTED_NVCTR_BASE UL(0xffe70000) |
laurenw-arm | 7c7b198 | 2020-10-21 13:34:40 -0500 | [diff] [blame] | 60 | #define TFW_NVCTR_BASE (TRUSTED_NVCTR_BASE + UL(0x0000)) |
| 61 | #define TFW_NVCTR_SIZE UL(4) |
| 62 | #define NTFW_CTR_BASE (TRUSTED_NVCTR_BASE + UL(0x0004)) |
| 63 | #define NTFW_CTR_SIZE UL(4) |
| 64 | |
| 65 | /* Keys */ |
Gary Morrison | 3d7f654 | 2021-01-27 13:08:47 -0600 | [diff] [blame] | 66 | #define SOC_KEYS_BASE UL(0xffe80000) |
laurenw-arm | 7c7b198 | 2020-10-21 13:34:40 -0500 | [diff] [blame] | 67 | #define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + UL(0x0000)) |
| 68 | #define TZ_PUB_KEY_HASH_SIZE UL(32) |
| 69 | #define HU_KEY_BASE (SOC_KEYS_BASE + UL(0x0020)) |
| 70 | #define HU_KEY_SIZE UL(16) |
| 71 | #define END_KEY_BASE (SOC_KEYS_BASE + UL(0x0044)) |
| 72 | #define END_KEY_SIZE UL(32) |
| 73 | |
| 74 | /* Constants to distinguish FVP_R type */ |
| 75 | #define HBI_BASE_FVP_R U(0x020) |
| 76 | #define REV_BASE_FVP_R_V0 U(0x0) |
| 77 | #define REV_BASE_FVP_R_REVC U(0x2) |
| 78 | |
| 79 | #define HBI_FOUNDATION_FVP_R U(0x010) |
| 80 | #define REV_FOUNDATION_FVP_R_V2_0 U(0x0) |
| 81 | #define REV_FOUNDATION_FVP_R_V2_1 U(0x1) |
| 82 | #define REV_FOUNDATION_FVP_R_v9_1 U(0x2) |
| 83 | #define REV_FOUNDATION_FVP_R_v9_6 U(0x3) |
| 84 | |
| 85 | #define BLD_GIC_VE_MMAP U(0x0) |
| 86 | #define BLD_GIC_A53A57_MMAP U(0x1) |
| 87 | |
| 88 | #define ARCH_MODEL U(0x1) |
| 89 | |
| 90 | /* FVP_R Power controller base address*/ |
| 91 | #define PWRC_BASE UL(0x1c100000) |
| 92 | |
| 93 | /* FVP_R SP804 timer frequency is 35 MHz*/ |
| 94 | #define SP804_TIMER_CLKMULT 1 |
| 95 | #define SP804_TIMER_CLKDIV 35 |
| 96 | |
| 97 | /* SP810 controller. FVP_R specific flags */ |
| 98 | #define FVP_R_SP810_CTRL_TIM0_OV BIT_32(16) |
| 99 | #define FVP_R_SP810_CTRL_TIM1_OV BIT_32(18) |
| 100 | #define FVP_R_SP810_CTRL_TIM2_OV BIT_32(20) |
| 101 | #define FVP_R_SP810_CTRL_TIM3_OV BIT_32(22) |
| 102 | |
| 103 | #endif /* FVP_R_DEF_H */ |