| Valentine Barshak | f218414 | 2018-10-30 02:06:17 +0300 | [diff] [blame] | 1 | /* |
| Marek Vasut | c73bad9 | 2019-06-17 19:10:05 +0200 | [diff] [blame^] | 2 | * Copyright (c) 2015-2019, Renesas Electronics Corporation |
| Valentine Barshak | f218414 | 2018-10-30 02:06:17 +0300 | [diff] [blame] | 3 | * All rights reserved. |
| 4 | * |
| 5 | * SPDX-License-Identifier: BSD-3-Clause |
| 6 | */ |
| 7 | |
| 8 | #include <stdint.h> /* for uint32_t */ |
| Ambroise Vincent | ffbf32a | 2019-03-28 09:01:18 +0000 | [diff] [blame] | 9 | #include <lib/mmio.h> |
| Valentine Barshak | f218414 | 2018-10-30 02:06:17 +0300 | [diff] [blame] | 10 | #include "pfc_init_v3m.h" |
| 11 | #include "include/rcar_def.h" |
| 12 | #include "rcar_private.h" |
| Marek Vasut | c73bad9 | 2019-06-17 19:10:05 +0200 | [diff] [blame^] | 13 | #include "../pfc_regs.h" |
| Valentine Barshak | f218414 | 2018-10-30 02:06:17 +0300 | [diff] [blame] | 14 | |
| 15 | /* Pin functon bit */ |
| 16 | #define GPSR0_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 21U) |
| 17 | #define GPSR0_DU_EXVSYNC_DU_VSYNC ((uint32_t)1U << 20U) |
| 18 | #define GPSR0_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 19U) |
| 19 | #define GPSR0_DU_DOTCLKOUT ((uint32_t)1U << 18U) |
| 20 | #define GPSR0_DU_DB7 ((uint32_t)1U << 17U) |
| 21 | #define GPSR0_DU_DB6 ((uint32_t)1U << 16U) |
| 22 | #define GPSR0_DU_DB5 ((uint32_t)1U << 15U) |
| 23 | #define GPSR0_DU_DB4 ((uint32_t)1U << 14U) |
| 24 | #define GPSR0_DU_DB3 ((uint32_t)1U << 13U) |
| 25 | #define GPSR0_DU_DB2 ((uint32_t)1U << 12U) |
| 26 | #define GPSR0_DU_DG7 ((uint32_t)1U << 11U) |
| 27 | #define GPSR0_DU_DG6 ((uint32_t)1U << 10U) |
| 28 | #define GPSR0_DU_DG5 ((uint32_t)1U << 9U) |
| 29 | #define GPSR0_DU_DG4 ((uint32_t)1U << 8U) |
| 30 | #define GPSR0_DU_DG3 ((uint32_t)1U << 7U) |
| 31 | #define GPSR0_DU_DG2 ((uint32_t)1U << 6U) |
| 32 | #define GPSR0_DU_DR7 ((uint32_t)1U << 5U) |
| 33 | #define GPSR0_DU_DR6 ((uint32_t)1U << 4U) |
| 34 | #define GPSR0_DU_DR5 ((uint32_t)1U << 3U) |
| 35 | #define GPSR0_DU_DR4 ((uint32_t)1U << 2U) |
| 36 | #define GPSR0_DU_DR3 ((uint32_t)1U << 1U) |
| 37 | #define GPSR0_DU_DR2 ((uint32_t)1U << 0U) |
| 38 | |
| 39 | #define GPSR1_DIGRF_CLKOUT ((uint32_t)1U << 27U) |
| 40 | #define GPSR1_DIGRF_CLKIN ((uint32_t)1U << 26U) |
| 41 | #define GPSR1_CANFD_CLK ((uint32_t)1U << 25U) |
| 42 | #define GPSR1_CANFD1_RX ((uint32_t)1U << 24U) |
| 43 | #define GPSR1_CANFD1_TX ((uint32_t)1U << 23U) |
| 44 | #define GPSR1_CANFD0_RX ((uint32_t)1U << 22U) |
| 45 | #define GPSR1_CANFD0_TX ((uint32_t)1U << 21U) |
| 46 | #define GPSR1_AVB0_AVTP_CAPTURE ((uint32_t)1U << 20U) |
| 47 | #define GPSR1_AVB0_AVTP_MATCH ((uint32_t)1U << 19U) |
| 48 | #define GPSR1_AVB0_LINK ((uint32_t)1U << 18U) |
| 49 | #define GPSR1_AVB0_PHY_INT ((uint32_t)1U << 17U) |
| 50 | #define GPSR1_AVB0_MAGIC ((uint32_t)1U << 16U) |
| 51 | #define GPSR1_AVB0_MDC ((uint32_t)1U << 15U) |
| 52 | #define GPSR1_AVB0_MDIO ((uint32_t)1U << 14U) |
| 53 | #define GPSR1_AVB0_TXCREFCLK ((uint32_t)1U << 13U) |
| 54 | #define GPSR1_AVB0_TD3 ((uint32_t)1U << 12U) |
| 55 | #define GPSR1_AVB0_TD2 ((uint32_t)1U << 11U) |
| 56 | #define GPSR1_AVB0_TD1 ((uint32_t)1U << 10U) |
| 57 | #define GPSR1_AVB0_TD0 ((uint32_t)1U << 9U) |
| 58 | #define GPSR1_AVB0_TXC ((uint32_t)1U << 8U) |
| 59 | #define GPSR1_AVB0_TX_CTL ((uint32_t)1U << 7U) |
| 60 | #define GPSR1_AVB0_RD3 ((uint32_t)1U << 6U) |
| 61 | #define GPSR1_AVB0_RD2 ((uint32_t)1U << 5U) |
| 62 | #define GPSR1_AVB0_RD1 ((uint32_t)1U << 4U) |
| 63 | #define GPSR1_AVB0_RD0 ((uint32_t)1U << 3U) |
| 64 | #define GPSR1_AVB0_RXC ((uint32_t)1U << 2U) |
| 65 | #define GPSR1_AVB0_RX_CTL ((uint32_t)1U << 1U) |
| 66 | #define GPSR1_IRQ0 ((uint32_t)1U << 0U) |
| 67 | |
| 68 | #define GPSR2_VI0_FIELD ((uint32_t)1U << 16U) |
| 69 | #define GPSR2_VI0_DATA11 ((uint32_t)1U << 15U) |
| 70 | #define GPSR2_VI0_DATA10 ((uint32_t)1U << 14U) |
| 71 | #define GPSR2_VI0_DATA9 ((uint32_t)1U << 13U) |
| 72 | #define GPSR2_VI0_DATA8 ((uint32_t)1U << 12U) |
| 73 | #define GPSR2_VI0_DATA7 ((uint32_t)1U << 11U) |
| 74 | #define GPSR2_VI0_DATA6 ((uint32_t)1U << 10U) |
| 75 | #define GPSR2_VI0_DATA5 ((uint32_t)1U << 9U) |
| 76 | #define GPSR2_VI0_DATA4 ((uint32_t)1U << 8U) |
| 77 | #define GPSR2_VI0_DATA3 ((uint32_t)1U << 7U) |
| 78 | #define GPSR2_VI0_DATA2 ((uint32_t)1U << 6U) |
| 79 | #define GPSR2_VI0_DATA1 ((uint32_t)1U << 5U) |
| 80 | #define GPSR2_VI0_DATA0 ((uint32_t)1U << 4U) |
| 81 | #define GPSR2_VI0_VSYNC_N ((uint32_t)1U << 3U) |
| 82 | #define GPSR2_VI0_HSYNC_N ((uint32_t)1U << 2U) |
| 83 | #define GPSR2_VI0_CLKENB ((uint32_t)1U << 1U) |
| 84 | #define GPSR2_VI0_CLK ((uint32_t)1U << 0U) |
| 85 | |
| 86 | #define GPSR3_VI1_FIELD ((uint32_t)1U << 16U) |
| 87 | #define GPSR3_VI1_DATA11 ((uint32_t)1U << 15U) |
| 88 | #define GPSR3_VI1_DATA10 ((uint32_t)1U << 14U) |
| 89 | #define GPSR3_VI1_DATA9 ((uint32_t)1U << 13U) |
| 90 | #define GPSR3_VI1_DATA8 ((uint32_t)1U << 12U) |
| 91 | #define GPSR3_VI1_DATA7 ((uint32_t)1U << 11U) |
| 92 | #define GPSR3_VI1_DATA6 ((uint32_t)1U << 10U) |
| 93 | #define GPSR3_VI1_DATA5 ((uint32_t)1U << 9U) |
| 94 | #define GPSR3_VI1_DATA4 ((uint32_t)1U << 8U) |
| 95 | #define GPSR3_VI1_DATA3 ((uint32_t)1U << 7U) |
| 96 | #define GPSR3_VI1_DATA2 ((uint32_t)1U << 6U) |
| 97 | #define GPSR3_VI1_DATA1 ((uint32_t)1U << 5U) |
| 98 | #define GPSR3_VI1_DATA0 ((uint32_t)1U << 4U) |
| 99 | #define GPSR3_VI1_VSYNC_N ((uint32_t)1U << 3U) |
| 100 | #define GPSR3_VI1_HSYNC_N ((uint32_t)1U << 2U) |
| 101 | #define GPSR3_VI1_CLKENB ((uint32_t)1U << 1U) |
| 102 | #define GPSR3_VI1_CLK ((uint32_t)1U << 0U) |
| 103 | |
| 104 | #define GPSR4_SDA2 ((uint32_t)1U << 5U) |
| 105 | #define GPSR4_SCL2 ((uint32_t)1U << 4U) |
| 106 | #define GPSR4_SDA1 ((uint32_t)1U << 3U) |
| 107 | #define GPSR4_SCL1 ((uint32_t)1U << 2U) |
| 108 | #define GPSR4_SDA0 ((uint32_t)1U << 1U) |
| 109 | #define GPSR4_SCL0 ((uint32_t)1U << 0U) |
| 110 | |
| 111 | #define GPSR5_RPC_INT_N ((uint32_t)1U << 14U) |
| 112 | #define GPSR5_RPC_WP_N ((uint32_t)1U << 13U) |
| 113 | #define GPSR5_RPC_RESET_N ((uint32_t)1U << 12U) |
| 114 | #define GPSR5_QSPI1_SSL ((uint32_t)1U << 11U) |
| 115 | #define GPSR5_QSPI1_IO3 ((uint32_t)1U << 10U) |
| 116 | #define GPSR5_QSPI1_IO2 ((uint32_t)1U << 9U) |
| 117 | #define GPSR5_QSPI1_MISO_IO1 ((uint32_t)1U << 8U) |
| 118 | #define GPSR5_QSPI1_MOSI_IO0 ((uint32_t)1U << 7U) |
| 119 | #define GPSR5_QSPI1_SPCLK ((uint32_t)1U << 6U) |
| 120 | #define GPSR5_QSPI0_SSL ((uint32_t)1U << 5U) |
| 121 | #define GPSR5_QSPI0_IO3 ((uint32_t)1U << 4U) |
| 122 | #define GPSR5_QSPI0_IO2 ((uint32_t)1U << 3U) |
| 123 | #define GPSR5_QSPI0_MISO_IO1 ((uint32_t)1U << 2U) |
| 124 | #define GPSR5_QSPI0_MOSI_IO0 ((uint32_t)1U << 1U) |
| 125 | #define GPSR5_QSPI0_SPCLK ((uint32_t)1U << 0U) |
| 126 | |
| 127 | #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U) |
| 128 | #define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U) |
| 129 | #define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U) |
| 130 | #define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U) |
| 131 | #define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U) |
| 132 | #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U) |
| 133 | #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U) |
| 134 | #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U) |
| 135 | |
| 136 | #define IOCTRL30_POC_VI0_DATA5 ((uint32_t)1U << 31U) |
| 137 | #define IOCTRL30_POC_VI0_DATA4 ((uint32_t)1U << 30U) |
| 138 | #define IOCTRL30_POC_VI0_DATA3 ((uint32_t)1U << 29U) |
| 139 | #define IOCTRL30_POC_VI0_DATA2 ((uint32_t)1U << 28U) |
| 140 | #define IOCTRL30_POC_VI0_DATA1 ((uint32_t)1U << 27U) |
| 141 | #define IOCTRL30_POC_VI0_DATA0 ((uint32_t)1U << 26U) |
| 142 | #define IOCTRL30_POC_VI0_VSYNC_N ((uint32_t)1U << 25U) |
| 143 | #define IOCTRL30_POC_VI0_HSYNC_N ((uint32_t)1U << 24U) |
| 144 | #define IOCTRL30_POC_VI0_CLKENB ((uint32_t)1U << 23U) |
| 145 | #define IOCTRL30_POC_VI0_CLK ((uint32_t)1U << 22U) |
| 146 | #define IOCTRL30_POC_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 21U) |
| 147 | #define IOCTRL30_POC_DU_EXVSYNC_DU_VSYNC ((uint32_t)1U << 20U) |
| 148 | #define IOCTRL30_POC_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 19U) |
| 149 | #define IOCTRL30_POC_DU_DOTCLKOUT ((uint32_t)1U << 18U) |
| 150 | #define IOCTRL30_POC_DU_DB7 ((uint32_t)1U << 17U) |
| 151 | #define IOCTRL30_POC_DU_DB6 ((uint32_t)1U << 16U) |
| 152 | #define IOCTRL30_POC_DU_DB5 ((uint32_t)1U << 15U) |
| 153 | #define IOCTRL30_POC_DU_DB4 ((uint32_t)1U << 14U) |
| 154 | #define IOCTRL30_POC_DU_DB3 ((uint32_t)1U << 13U) |
| 155 | #define IOCTRL30_POC_DU_DB2 ((uint32_t)1U << 12U) |
| 156 | #define IOCTRL30_POC_DU_DG7 ((uint32_t)1U << 11U) |
| 157 | #define IOCTRL30_POC_DU_DG6 ((uint32_t)1U << 10U) |
| 158 | #define IOCTRL30_POC_DU_DG5 ((uint32_t)1U << 9U) |
| 159 | #define IOCTRL30_POC_DU_DG4 ((uint32_t)1U << 8U) |
| 160 | #define IOCTRL30_POC_DU_DG3 ((uint32_t)1U << 7U) |
| 161 | #define IOCTRL30_POC_DU_DG2 ((uint32_t)1U << 6U) |
| 162 | #define IOCTRL30_POC_DU_DR7 ((uint32_t)1U << 5U) |
| 163 | #define IOCTRL30_POC_DU_DR6 ((uint32_t)1U << 4U) |
| 164 | #define IOCTRL30_POC_DU_DR5 ((uint32_t)1U << 3U) |
| 165 | #define IOCTRL30_POC_DU_DR4 ((uint32_t)1U << 2U) |
| 166 | #define IOCTRL30_POC_DU_DR3 ((uint32_t)1U << 1U) |
| 167 | #define IOCTRL30_POC_DU_DR2 ((uint32_t)1U << 0U) |
| 168 | |
| 169 | #define IOCTRL31_POC_DUMMY_31 ((uint32_t)1U << 31U) |
| 170 | #define IOCTRL31_POC_DUMMY_30 ((uint32_t)1U << 30U) |
| 171 | #define IOCTRL31_POC_DUMMY_29 ((uint32_t)1U << 29U) |
| 172 | #define IOCTRL31_POC_DUMMY_28 ((uint32_t)1U << 28U) |
| 173 | #define IOCTRL31_POC_DUMMY_27 ((uint32_t)1U << 27U) |
| 174 | #define IOCTRL31_POC_DUMMY_26 ((uint32_t)1U << 26U) |
| 175 | #define IOCTRL31_POC_DUMMY_25 ((uint32_t)1U << 25U) |
| 176 | #define IOCTRL31_POC_DUMMY_24 ((uint32_t)1U << 24U) |
| 177 | #define IOCTRL31_POC_VI1_FIELD ((uint32_t)1U << 23U) |
| 178 | #define IOCTRL31_POC_VI1_DATA11 ((uint32_t)1U << 22U) |
| 179 | #define IOCTRL31_POC_VI1_DATA10 ((uint32_t)1U << 21U) |
| 180 | #define IOCTRL31_POC_VI1_DATA9 ((uint32_t)1U << 20U) |
| 181 | #define IOCTRL31_POC_VI1_DATA8 ((uint32_t)1U << 19U) |
| 182 | #define IOCTRL31_POC_VI1_DATA7 ((uint32_t)1U << 18U) |
| 183 | #define IOCTRL31_POC_VI1_DATA6 ((uint32_t)1U << 17U) |
| 184 | #define IOCTRL31_POC_VI1_DATA5 ((uint32_t)1U << 16U) |
| 185 | #define IOCTRL31_POC_VI1_DATA4 ((uint32_t)1U << 15U) |
| 186 | #define IOCTRL31_POC_VI1_DATA3 ((uint32_t)1U << 14U) |
| 187 | #define IOCTRL31_POC_VI1_DATA2 ((uint32_t)1U << 13U) |
| 188 | #define IOCTRL31_POC_VI1_DATA1 ((uint32_t)1U << 12U) |
| 189 | #define IOCTRL31_POC_VI1_DATA0 ((uint32_t)1U << 11U) |
| 190 | #define IOCTRL31_POC_VI1_VSYNC_N ((uint32_t)1U << 10U) |
| 191 | #define IOCTRL31_POC_VI1_HSYNC_N ((uint32_t)1U << 9U) |
| 192 | #define IOCTRL31_POC_VI1_CLKENB ((uint32_t)1U << 8U) |
| 193 | #define IOCTRL31_POC_VI1_CLK ((uint32_t)1U << 7U) |
| 194 | #define IOCTRL31_POC_VI0_FIELD ((uint32_t)1U << 6U) |
| 195 | #define IOCTRL31_POC_VI0_DATA11 ((uint32_t)1U << 5U) |
| 196 | #define IOCTRL31_POC_VI0_DATA10 ((uint32_t)1U << 4U) |
| 197 | #define IOCTRL31_POC_VI0_DATA9 ((uint32_t)1U << 3U) |
| 198 | #define IOCTRL31_POC_VI0_DATA8 ((uint32_t)1U << 2U) |
| 199 | #define IOCTRL31_POC_VI0_DATA7 ((uint32_t)1U << 1U) |
| 200 | #define IOCTRL31_POC_VI0_DATA6 ((uint32_t)1U << 0U) |
| 201 | #define IOCTRL32_POC2_VREF ((uint32_t)1U << 0U) |
| 202 | #define IOCTRL40_SD0TDSEL1 ((uint32_t)1U << 1U) |
| 203 | #define IOCTRL40_SD0TDSEL0 ((uint32_t)1U << 0U) |
| 204 | |
| 205 | #define PUEN0_PUEN_VI0_CLK ((uint32_t)1U << 31U) |
| 206 | #define PUEN0_PUEN_TDI ((uint32_t)1U << 30U) |
| 207 | #define PUEN0_PUEN_TMS ((uint32_t)1U << 29U) |
| 208 | #define PUEN0_PUEN_TCK ((uint32_t)1U << 28U) |
| 209 | #define PUEN0_PUEN_TRST_N ((uint32_t)1U << 27U) |
| 210 | #define PUEN0_PUEN_IRQ0 ((uint32_t)1U << 26U) |
| 211 | #define PUEN0_PUEN_FSCLKST_N ((uint32_t)1U << 25U) |
| 212 | #define PUEN0_PUEN_EXTALR ((uint32_t)1U << 24U) |
| 213 | #define PUEN0_PUEN_PRESETOUT_N ((uint32_t)1U << 23U) |
| 214 | #define PUEN0_PUEN_DU_DOTCLKIN ((uint32_t)1U << 22U) |
| 215 | #define PUEN0_PUEN_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 21U) |
| 216 | #define PUEN0_PUEN_DU_EXVSYNC_DU_VSYNC ((uint32_t)1U << 20U) |
| 217 | #define PUEN0_PUEN_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 19U) |
| 218 | #define PUEN0_PUEN_DU_DOTCLKOUT ((uint32_t)1U << 18U) |
| 219 | #define PUEN0_PUEN_DU_DB7 ((uint32_t)1U << 17U) |
| 220 | #define PUEN0_PUEN_DU_DB6 ((uint32_t)1U << 16U) |
| 221 | #define PUEN0_PUEN_DU_DB5 ((uint32_t)1U << 15U) |
| 222 | #define PUEN0_PUEN_DU_DB4 ((uint32_t)1U << 14U) |
| 223 | #define PUEN0_PUEN_DU_DB3 ((uint32_t)1U << 13U) |
| 224 | #define PUEN0_PUEN_DU_DB2 ((uint32_t)1U << 12U) |
| 225 | #define PUEN0_PUEN_DU_DG7 ((uint32_t)1U << 11U) |
| 226 | #define PUEN0_PUEN_DU_DG6 ((uint32_t)1U << 10U) |
| 227 | #define PUEN0_PUEN_DU_DG5 ((uint32_t)1U << 9U) |
| 228 | #define PUEN0_PUEN_DU_DG4 ((uint32_t)1U << 8U) |
| 229 | #define PUEN0_PUEN_DU_DG3 ((uint32_t)1U << 7U) |
| 230 | #define PUEN0_PUEN_DU_DG2 ((uint32_t)1U << 6U) |
| 231 | #define PUEN0_PUEN_DU_DR7 ((uint32_t)1U << 5U) |
| 232 | #define PUEN0_PUEN_DU_DR6 ((uint32_t)1U << 4U) |
| 233 | #define PUEN0_PUEN_DU_DR5 ((uint32_t)1U << 3U) |
| 234 | #define PUEN0_PUEN_DU_DR4 ((uint32_t)1U << 2U) |
| 235 | #define PUEN0_PUEN_DU_DR3 ((uint32_t)1U << 1U) |
| 236 | #define PUEN0_PUEN_DU_DR2 ((uint32_t)1U << 0U) |
| 237 | |
| 238 | #define PUEN1_PUEN_VI1_DATA11 ((uint32_t)1U << 31U) |
| 239 | #define PUEN1_PUEN_VI1_DATA10 ((uint32_t)1U << 30U) |
| 240 | #define PUEN1_PUEN_VI1_DATA9 ((uint32_t)1U << 29U) |
| 241 | #define PUEN1_PUEN_VI1_DATA8 ((uint32_t)1U << 28U) |
| 242 | #define PUEN1_PUEN_VI1_DATA7 ((uint32_t)1U << 27U) |
| 243 | #define PUEN1_PUEN_VI1_DATA6 ((uint32_t)1U << 26U) |
| 244 | #define PUEN1_PUEN_VI1_DATA5 ((uint32_t)1U << 25U) |
| 245 | #define PUEN1_PUEN_VI1_DATA4 ((uint32_t)1U << 24U) |
| 246 | #define PUEN1_PUEN_VI1_DATA3 ((uint32_t)1U << 23U) |
| 247 | #define PUEN1_PUEN_VI1_DATA2 ((uint32_t)1U << 22U) |
| 248 | #define PUEN1_PUEN_VI1_DATA1 ((uint32_t)1U << 21U) |
| 249 | #define PUEN1_PUEN_VI1_DATA0 ((uint32_t)1U << 20U) |
| 250 | #define PUEN1_PUEN_VI1_VSYNC_N ((uint32_t)1U << 19U) |
| 251 | #define PUEN1_PUEN_VI1_HSYNC_N ((uint32_t)1U << 18U) |
| 252 | #define PUEN1_PUEN_VI1_CLKENB ((uint32_t)1U << 17U) |
| 253 | #define PUEN1_PUEN_VI1_CLK ((uint32_t)1U << 16U) |
| 254 | #define PUEN1_PUEN_VI0_FIELD ((uint32_t)1U << 15U) |
| 255 | #define PUEN1_PUEN_VI0_DATA11 ((uint32_t)1U << 14U) |
| 256 | #define PUEN1_PUEN_VI0_DATA10 ((uint32_t)1U << 13U) |
| 257 | #define PUEN1_PUEN_VI0_DATA9 ((uint32_t)1U << 12U) |
| 258 | #define PUEN1_PUEN_VI0_DATA8 ((uint32_t)1U << 11U) |
| 259 | #define PUEN1_PUEN_VI0_DATA7 ((uint32_t)1U << 10U) |
| 260 | #define PUEN1_PUEN_VI0_DATA6 ((uint32_t)1U << 9U) |
| 261 | #define PUEN1_PUEN_VI0_DATA5 ((uint32_t)1U << 8U) |
| 262 | #define PUEN1_PUEN_VI0_DATA4 ((uint32_t)1U << 7U) |
| 263 | #define PUEN1_PUEN_VI0_DATA3 ((uint32_t)1U << 6U) |
| 264 | #define PUEN1_PUEN_VI0_DATA2 ((uint32_t)1U << 5U) |
| 265 | #define PUEN1_PUEN_VI0_DATA1 ((uint32_t)1U << 4U) |
| 266 | #define PUEN1_PUEN_VI0_DATA0 ((uint32_t)1U << 3U) |
| 267 | #define PUEN1_PUEN_VI0_VSYNC_N ((uint32_t)1U << 2U) |
| 268 | #define PUEN1_PUEN_VI0_HSYNC_N ((uint32_t)1U << 1U) |
| 269 | #define PUEN1_PUEN_VI0_CLKENB ((uint32_t)1U << 0U) |
| 270 | |
| 271 | #define PUEN2_PUEN_CANFD_CLK ((uint32_t)1U << 31U) |
| 272 | #define PUEN2_PUEN_CANFD1_RX ((uint32_t)1U << 30U) |
| 273 | #define PUEN2_PUEN_CANFD1_TX ((uint32_t)1U << 29U) |
| 274 | #define PUEN2_PUEN_CANFD0_RX ((uint32_t)1U << 28U) |
| 275 | #define PUEN2_PUEN_CANFD0_TX ((uint32_t)1U << 27U) |
| 276 | #define PUEN2_PUEN_AVB0_AVTP_CAPTURE ((uint32_t)1U << 26U) |
| 277 | #define PUEN2_PUEN_AVB0_AVTP_MATCH ((uint32_t)1U << 25U) |
| 278 | #define PUEN2_PUEN_AVB0_LINK ((uint32_t)1U << 24U) |
| 279 | #define PUEN2_PUEN_AVB0_PHY_INT ((uint32_t)1U << 23U) |
| 280 | #define PUEN2_PUEN_AVB0_MAGIC ((uint32_t)1U << 22U) |
| 281 | #define PUEN2_PUEN_AVB0_MDC ((uint32_t)1U << 21U) |
| 282 | #define PUEN2_PUEN_AVB0_MDIO ((uint32_t)1U << 20U) |
| 283 | #define PUEN2_PUEN_AVB0_TXCREFCLK ((uint32_t)1U << 19U) |
| 284 | #define PUEN2_PUEN_AVB0_TD3 ((uint32_t)1U << 18U) |
| 285 | #define PUEN2_PUEN_AVB0_TD2 ((uint32_t)1U << 17U) |
| 286 | #define PUEN2_PUEN_AVB0_TD1 ((uint32_t)1U << 16U) |
| 287 | #define PUEN2_PUEN_AVB0_TD0 ((uint32_t)1U << 15U) |
| 288 | #define PUEN2_PUEN_AVB0_TXC ((uint32_t)1U << 14U) |
| 289 | #define PUEN2_PUEN_AVB0_TX_CTL ((uint32_t)1U << 13U) |
| 290 | #define PUEN2_PUEN_AVB0_RD3 ((uint32_t)1U << 12U) |
| 291 | #define PUEN2_PUEN_AVB0_RD2 ((uint32_t)1U << 11U) |
| 292 | #define PUEN2_PUEN_AVB0_RD1 ((uint32_t)1U << 10U) |
| 293 | #define PUEN2_PUEN_AVB0_RD0 ((uint32_t)1U << 9U) |
| 294 | #define PUEN2_PUEN_AVB0_RXC ((uint32_t)1U << 8U) |
| 295 | #define PUEN2_PUEN_AVB0_RX_CTL ((uint32_t)1U << 7U) |
| 296 | #define PUEN2_PUEN_SDA2 ((uint32_t)1U << 6U) |
| 297 | #define PUEN2_PUEN_SCL2 ((uint32_t)1U << 5U) |
| 298 | #define PUEN2_PUEN_SDA1 ((uint32_t)1U << 4U) |
| 299 | #define PUEN2_PUEN_SCL1 ((uint32_t)1U << 3U) |
| 300 | #define PUEN2_PUEN_SDA0 ((uint32_t)1U << 2U) |
| 301 | #define PUEN2_PUEN_SCL0 ((uint32_t)1U << 1U) |
| 302 | #define PUEN2_PUEN_VI1_FIELD ((uint32_t)1U << 0U) |
| 303 | |
| 304 | #define PUEN3_PUEN_DIGRF_CLKOUT ((uint32_t)1U << 16U) |
| 305 | #define PUEN3_PUEN_DIGRF_CLKIN ((uint32_t)1U << 15U) |
| 306 | #define PUEN3_PUEN_RPC_INT_N ((uint32_t)1U << 14U) |
| 307 | #define PUEN3_PUEN_RPC_WP_N ((uint32_t)1U << 13U) |
| 308 | #define PUEN3_PUEN_RPC_RESET_N ((uint32_t)1U << 12U) |
| 309 | #define PUEN3_PUEN_QSPI1_SSL ((uint32_t)1U << 11U) |
| 310 | #define PUEN3_PUEN_QSPI1_IO3 ((uint32_t)1U << 10U) |
| 311 | #define PUEN3_PUEN_QSPI1_IO2 ((uint32_t)1U << 9U) |
| 312 | #define PUEN3_PUEN_QSPI1_MISO_IO1 ((uint32_t)1U << 8U) |
| 313 | #define PUEN3_PUEN_QSPI1_MOSI_IO0 ((uint32_t)1U << 7U) |
| 314 | #define PUEN3_PUEN_QSPI1_SPCLK ((uint32_t)1U << 6U) |
| 315 | #define PUEN3_PUEN_QSPI0_SSL ((uint32_t)1U << 5U) |
| 316 | #define PUEN3_PUEN_QSPI0_IO3 ((uint32_t)1U << 4U) |
| 317 | #define PUEN3_PUEN_QSPI0_IO2 ((uint32_t)1U << 3U) |
| 318 | #define PUEN3_PUEN_QSPI0_MISO_IO1 ((uint32_t)1U << 2U) |
| 319 | #define PUEN3_PUEN_QSPI0_MOSI_IO0 ((uint32_t)1U << 1U) |
| 320 | #define PUEN3_PUEN_QSPI0_SPCLK ((uint32_t)1U << 0U) |
| 321 | |
| 322 | #define PUD0_PUD_VI0_CLK ((uint32_t)1U << 31U) |
| 323 | #define PUD0_PUD_IRQ0 ((uint32_t)1U << 26U) |
| 324 | #define PUD0_PUD_FSCLKST_N ((uint32_t)1U << 25U) |
| 325 | #define PUD0_PUD_PRESETOUT_N ((uint32_t)1U << 23U) |
| 326 | #define PUD0_PUD_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 21U) |
| 327 | #define PUD0_PUD_DU_EXVSYNC_DU_VSYNC ((uint32_t)1U << 20U) |
| 328 | #define PUD0_PUD_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 19U) |
| 329 | #define PUD0_PUD_DU_DOTCLKOUT ((uint32_t)1U << 18U) |
| 330 | #define PUD0_PUD_DU_DB7 ((uint32_t)1U << 17U) |
| 331 | #define PUD0_PUD_DU_DB6 ((uint32_t)1U << 16U) |
| 332 | #define PUD0_PUD_DU_DB5 ((uint32_t)1U << 15U) |
| 333 | #define PUD0_PUD_DU_DB4 ((uint32_t)1U << 14U) |
| 334 | #define PUD0_PUD_DU_DB3 ((uint32_t)1U << 13U) |
| 335 | #define PUD0_PUD_DU_DB2 ((uint32_t)1U << 12U) |
| 336 | #define PUD0_PUD_DU_DG7 ((uint32_t)1U << 11U) |
| 337 | #define PUD0_PUD_DU_DG6 ((uint32_t)1U << 10U) |
| 338 | #define PUD0_PUD_DU_DG5 ((uint32_t)1U << 9U) |
| 339 | #define PUD0_PUD_DU_DG4 ((uint32_t)1U << 8U) |
| 340 | #define PUD0_PUD_DU_DG3 ((uint32_t)1U << 7U) |
| 341 | #define PUD0_PUD_DU_DG2 ((uint32_t)1U << 6U) |
| 342 | #define PUD0_PUD_DU_DR7 ((uint32_t)1U << 5U) |
| 343 | #define PUD0_PUD_DU_DR6 ((uint32_t)1U << 4U) |
| 344 | #define PUD0_PUD_DU_DR5 ((uint32_t)1U << 3U) |
| 345 | #define PUD0_PUD_DU_DR4 ((uint32_t)1U << 2U) |
| 346 | #define PUD0_PUD_DU_DR3 ((uint32_t)1U << 1U) |
| 347 | #define PUD0_PUD_DU_DR2 ((uint32_t)1U << 0U) |
| 348 | |
| 349 | #define PUD1_PUD_VI1_DATA11 ((uint32_t)1U << 31U) |
| 350 | #define PUD1_PUD_VI1_DATA10 ((uint32_t)1U << 30U) |
| 351 | #define PUD1_PUD_VI1_DATA9 ((uint32_t)1U << 29U) |
| 352 | #define PUD1_PUD_VI1_DATA8 ((uint32_t)1U << 28U) |
| 353 | #define PUD1_PUD_VI1_DATA7 ((uint32_t)1U << 27U) |
| 354 | #define PUD1_PUD_VI1_DATA6 ((uint32_t)1U << 26U) |
| 355 | #define PUD1_PUD_VI1_DATA5 ((uint32_t)1U << 25U) |
| 356 | #define PUD1_PUD_VI1_DATA4 ((uint32_t)1U << 24U) |
| 357 | #define PUD1_PUD_VI1_DATA3 ((uint32_t)1U << 23U) |
| 358 | #define PUD1_PUD_VI1_DATA2 ((uint32_t)1U << 22U) |
| 359 | #define PUD1_PUD_VI1_DATA1 ((uint32_t)1U << 21U) |
| 360 | #define PUD1_PUD_VI1_DATA0 ((uint32_t)1U << 20U) |
| 361 | #define PUD1_PUD_VI1_VSYNC_N ((uint32_t)1U << 19U) |
| 362 | #define PUD1_PUD_VI1_HSYNC_N ((uint32_t)1U << 18U) |
| 363 | #define PUD1_PUD_VI1_CLKENB ((uint32_t)1U << 17U) |
| 364 | #define PUD1_PUD_VI1_CLK ((uint32_t)1U << 16U) |
| 365 | #define PUD1_PUD_VI0_FIELD ((uint32_t)1U << 15U) |
| 366 | #define PUD1_PUD_VI0_DATA11 ((uint32_t)1U << 14U) |
| 367 | #define PUD1_PUD_VI0_DATA10 ((uint32_t)1U << 13U) |
| 368 | #define PUD1_PUD_VI0_DATA9 ((uint32_t)1U << 12U) |
| 369 | #define PUD1_PUD_VI0_DATA8 ((uint32_t)1U << 11U) |
| 370 | #define PUD1_PUD_VI0_DATA7 ((uint32_t)1U << 10U) |
| 371 | #define PUD1_PUD_VI0_DATA6 ((uint32_t)1U << 9U) |
| 372 | #define PUD1_PUD_VI0_DATA5 ((uint32_t)1U << 8U) |
| 373 | #define PUD1_PUD_VI0_DATA4 ((uint32_t)1U << 7U) |
| 374 | #define PUD1_PUD_VI0_DATA3 ((uint32_t)1U << 6U) |
| 375 | #define PUD1_PUD_VI0_DATA2 ((uint32_t)1U << 5U) |
| 376 | #define PUD1_PUD_VI0_DATA1 ((uint32_t)1U << 4U) |
| 377 | #define PUD1_PUD_VI0_DATA0 ((uint32_t)1U << 3U) |
| 378 | #define PUD1_PUD_VI0_VSYNC_N ((uint32_t)1U << 2U) |
| 379 | #define PUD1_PUD_VI0_HSYNC_N ((uint32_t)1U << 1U) |
| 380 | #define PUD1_PUD_VI0_CLKENB ((uint32_t)1U << 0U) |
| 381 | |
| 382 | #define PUD2_PUD_CANFD_CLK ((uint32_t)1U << 31U) |
| 383 | #define PUD2_PUD_CANFD1_RX ((uint32_t)1U << 30U) |
| 384 | #define PUD2_PUD_CANFD1_TX ((uint32_t)1U << 29U) |
| 385 | #define PUD2_PUD_CANFD0_RX ((uint32_t)1U << 28U) |
| 386 | #define PUD2_PUD_CANFD0_TX ((uint32_t)1U << 27U) |
| 387 | #define PUD2_PUD_AVB0_AVTP_CAPTURE ((uint32_t)1U << 26U) |
| 388 | #define PUD2_PUD_AVB0_AVTP_MATCH ((uint32_t)1U << 25U) |
| 389 | #define PUD2_PUD_AVB0_LINK ((uint32_t)1U << 24U) |
| 390 | #define PUD2_PUD_AVB0_PHY_INT ((uint32_t)1U << 23U) |
| 391 | #define PUD2_PUD_AVB0_MAGIC ((uint32_t)1U << 22U) |
| 392 | #define PUD2_PUD_AVB0_MDC ((uint32_t)1U << 21U) |
| 393 | #define PUD2_PUD_AVB0_MDIO ((uint32_t)1U << 20U) |
| 394 | #define PUD2_PUD_AVB0_TXCREFCLK ((uint32_t)1U << 19U) |
| 395 | #define PUD2_PUD_AVB0_TD3 ((uint32_t)1U << 18U) |
| 396 | #define PUD2_PUD_AVB0_TD2 ((uint32_t)1U << 17U) |
| 397 | #define PUD2_PUD_AVB0_TD1 ((uint32_t)1U << 16U) |
| 398 | #define PUD2_PUD_AVB0_TD0 ((uint32_t)1U << 15U) |
| 399 | #define PUD2_PUD_AVB0_TXC ((uint32_t)1U << 14U) |
| 400 | #define PUD2_PUD_AVB0_TX_CTL ((uint32_t)1U << 13U) |
| 401 | #define PUD2_PUD_AVB0_RD3 ((uint32_t)1U << 12U) |
| 402 | #define PUD2_PUD_AVB0_RD2 ((uint32_t)1U << 11U) |
| 403 | #define PUD2_PUD_AVB0_RD1 ((uint32_t)1U << 10U) |
| 404 | #define PUD2_PUD_AVB0_RD0 ((uint32_t)1U << 9U) |
| 405 | #define PUD2_PUD_AVB0_RXC ((uint32_t)1U << 8U) |
| 406 | #define PUD2_PUD_AVB0_RX_CTL ((uint32_t)1U << 7U) |
| 407 | #define PUD2_PUD_SDA2 ((uint32_t)1U << 6U) |
| 408 | #define PUD2_PUD_SCL2 ((uint32_t)1U << 5U) |
| 409 | #define PUD2_PUD_SDA1 ((uint32_t)1U << 4U) |
| 410 | #define PUD2_PUD_SCL1 ((uint32_t)1U << 3U) |
| 411 | #define PUD2_PUD_SDA0 ((uint32_t)1U << 2U) |
| 412 | #define PUD2_PUD_SCL0 ((uint32_t)1U << 1U) |
| 413 | #define PUD2_PUD_VI1_FIELD ((uint32_t)1U << 0U) |
| 414 | |
| 415 | #define PUD3_PUD_DIGRF_CLKOUT ((uint32_t)1U << 16U) |
| 416 | #define PUD3_PUD_DIGRF_CLKIN ((uint32_t)1U << 15U) |
| 417 | #define PUD3_PUD_RPC_INT_N ((uint32_t)1U << 14U) |
| 418 | #define PUD3_PUD_RPC_WP_N ((uint32_t)1U << 13U) |
| 419 | #define PUD3_PUD_RPC_RESET_N ((uint32_t)1U << 12U) |
| 420 | #define PUD3_PUD_QSPI1_SSL ((uint32_t)1U << 11U) |
| 421 | #define PUD3_PUD_QSPI1_IO3 ((uint32_t)1U << 10U) |
| 422 | #define PUD3_PUD_QSPI1_IO2 ((uint32_t)1U << 9U) |
| 423 | #define PUD3_PUD_QSPI1_MISO_IO1 ((uint32_t)1U << 8U) |
| 424 | #define PUD3_PUD_QSPI1_MOSI_IO0 ((uint32_t)1U << 7U) |
| 425 | #define PUD3_PUD_QSPI1_SPCLK ((uint32_t)1U << 6U) |
| 426 | #define PUD3_PUD_QSPI0_SSL ((uint32_t)1U << 5U) |
| 427 | #define PUD3_PUD_QSPI0_IO3 ((uint32_t)1U << 4U) |
| 428 | #define PUD3_PUD_QSPI0_IO2 ((uint32_t)1U << 3U) |
| 429 | #define PUD3_PUD_QSPI0_MISO_IO1 ((uint32_t)1U << 2U) |
| 430 | #define PUD3_PUD_QSPI0_MOSI_IO0 ((uint32_t)1U << 1U) |
| 431 | #define PUD3_PUD_QSPI0_SPCLK ((uint32_t)1U << 0U) |
| 432 | |
| 433 | #define MOD_SEL0_sel_hscif0 ((uint32_t)1U << 10U) |
| 434 | #define MOD_SEL0_sel_scif1 ((uint32_t)1U << 9U) |
| 435 | #define MOD_SEL0_sel_canfd0 ((uint32_t)1U << 8U) |
| 436 | #define MOD_SEL0_sel_pwm4 ((uint32_t)1U << 7U) |
| 437 | #define MOD_SEL0_sel_pwm3 ((uint32_t)1U << 6U) |
| 438 | #define MOD_SEL0_sel_pwm2 ((uint32_t)1U << 5U) |
| 439 | #define MOD_SEL0_sel_pwm1 ((uint32_t)1U << 4U) |
| 440 | #define MOD_SEL0_sel_pwm0 ((uint32_t)1U << 3U) |
| 441 | #define MOD_SEL0_sel_rfso ((uint32_t)1U << 2U) |
| 442 | #define MOD_SEL0_sel_rsp ((uint32_t)1U << 1U) |
| 443 | #define MOD_SEL0_sel_tmu ((uint32_t)1U << 0U) |
| 444 | |
| 445 | /* SCIF3 Registers for Dummy write */ |
| 446 | #define SCIF3_BASE (0xE6C50000U) |
| 447 | #define SCIF3_SCFCR (SCIF3_BASE + 0x0018U) |
| 448 | #define SCIF3_SCFDR (SCIF3_BASE + 0x001CU) |
| 449 | #define SCFCR_DATA (0x0000U) |
| 450 | |
| 451 | /* Realtime module stop control */ |
| 452 | #define CPG_BASE (0xE6150000U) |
| 453 | #define CPG_MSTPSR0 (CPG_BASE + 0x0030U) |
| 454 | #define CPG_RMSTPCR0 (CPG_BASE + 0x0110U) |
| 455 | #define RMSTPCR0_RTDMAC (0x00200000U) |
| 456 | |
| 457 | /* RT-DMAC Registers */ |
| 458 | #define RTDMAC_CH (0U) /* choose 0 to 15 */ |
| 459 | |
| 460 | #define RTDMAC_BASE (0xFFC10000U) |
| 461 | #define RTDMAC_RDMOR (RTDMAC_BASE + 0x0060U) |
| 462 | #define RTDMAC_RDMCHCLR (RTDMAC_BASE + 0x0080U) |
| 463 | #define RTDMAC_RDMSAR(x) (RTDMAC_BASE + 0x8000U + (0x80U * (x))) |
| 464 | #define RTDMAC_RDMDAR(x) (RTDMAC_BASE + 0x8004U + (0x80U * (x))) |
| 465 | #define RTDMAC_RDMTCR(x) (RTDMAC_BASE + 0x8008U + (0x80U * (x))) |
| 466 | #define RTDMAC_RDMCHCR(x) (RTDMAC_BASE + 0x800CU + (0x80U * (x))) |
| 467 | #define RTDMAC_RDMCHCRB(x) (RTDMAC_BASE + 0x801CU + (0x80U * (x))) |
| 468 | #define RTDMAC_RDMDPBASE(x) (RTDMAC_BASE + 0x8050U + (0x80U * (x))) |
| 469 | #define RTDMAC_DESC_BASE (RTDMAC_BASE + 0xA000U) |
| 470 | #define RTDMAC_DESC_RDMSAR (RTDMAC_DESC_BASE + 0x0000U) |
| 471 | #define RTDMAC_DESC_RDMDAR (RTDMAC_DESC_BASE + 0x0004U) |
| 472 | #define RTDMAC_DESC_RDMTCR (RTDMAC_DESC_BASE + 0x0008U) |
| 473 | |
| 474 | #define RDMOR_DME (0x0001U) /* DMA Master Enable */ |
| 475 | #define RDMCHCR_DPM_INFINITE (0x30000000U) /* Infinite repeat mode */ |
| 476 | #define RDMCHCR_RPT_TCR (0x02000000U) /* enable to update TCR */ |
| 477 | #define RDMCHCR_TS_2 (0x00000008U) /* Word(2byte) units transfer */ |
| 478 | #define RDMCHCR_RS_AUTO (0x00000400U) /* Auto request */ |
| 479 | #define RDMCHCR_DE (0x00000001U) /* DMA Enable */ |
| 480 | #define RDMCHCRB_DRST (0x00008000U) /* Descriptor reset */ |
| 481 | #define RDMCHCRB_SLM_256 (0x00000080U) /* once in 256 clock cycle */ |
| 482 | #define RDMDPBASE_SEL_EXT (0x00000001U) /* External memory use */ |
| 483 | |
| 484 | static void pfc_reg_write(uint32_t addr, uint32_t data); |
| 485 | static void StartRtDma0_Descriptor(void); |
| 486 | |
| 487 | static void pfc_reg_write(uint32_t addr, uint32_t data) |
| 488 | { |
| 489 | mmio_write_32(PFC_PMMR, ~data); |
| 490 | mmio_write_32((uintptr_t)addr, data); |
| 491 | } |
| 492 | |
| 493 | static void StartRtDma0_Descriptor(void) |
| 494 | { |
| 495 | uint32_t reg; |
| 496 | |
| 497 | /* Module stop clear */ |
| 498 | while((mmio_read_32(CPG_MSTPSR0) & RMSTPCR0_RTDMAC) != 0U) { |
| 499 | reg = mmio_read_32(CPG_RMSTPCR0); |
| 500 | reg &= ~RMSTPCR0_RTDMAC; |
| 501 | cpg_write(CPG_RMSTPCR0, reg); |
| 502 | } |
| 503 | |
| 504 | /* Initialize ch0, Reset Descriptor */ |
| 505 | mmio_write_32(RTDMAC_RDMCHCLR, ((uint32_t)1U << RTDMAC_CH)); |
| 506 | mmio_write_32(RTDMAC_RDMCHCRB(RTDMAC_CH), RDMCHCRB_DRST); |
| 507 | |
| 508 | /* Enable DMA */ |
| 509 | mmio_write_16(RTDMAC_RDMOR, RDMOR_DME); |
| 510 | |
| 511 | /* Set first transfer */ |
| 512 | mmio_write_32(RTDMAC_RDMSAR(RTDMAC_CH), RCAR_PRR); |
| 513 | mmio_write_32(RTDMAC_RDMDAR(RTDMAC_CH), SCIF3_SCFDR); |
| 514 | mmio_write_32(RTDMAC_RDMTCR(RTDMAC_CH), 0x00000001U); |
| 515 | |
| 516 | /* Set descriptor */ |
| 517 | mmio_write_32(RTDMAC_DESC_RDMSAR, 0x00000000U); |
| 518 | mmio_write_32(RTDMAC_DESC_RDMDAR, 0x00000000U); |
| 519 | mmio_write_32(RTDMAC_DESC_RDMTCR, 0x00200000U); |
| 520 | mmio_write_32(RTDMAC_RDMCHCRB(RTDMAC_CH), RDMCHCRB_SLM_256); |
| 521 | mmio_write_32(RTDMAC_RDMDPBASE(RTDMAC_CH), RTDMAC_DESC_BASE |
| 522 | | RDMDPBASE_SEL_EXT); |
| 523 | |
| 524 | /* Set transfer parameter, Start transfer */ |
| 525 | mmio_write_32(RTDMAC_RDMCHCR(RTDMAC_CH), RDMCHCR_DPM_INFINITE |
| 526 | | RDMCHCR_RPT_TCR |
| 527 | | RDMCHCR_TS_2 |
| 528 | | RDMCHCR_RS_AUTO |
| 529 | | RDMCHCR_DE); |
| 530 | } |
| 531 | |
| 532 | void pfc_init_v3m(void) |
| 533 | { |
| 534 | /* Work around for PFC eratta */ |
| 535 | StartRtDma0_Descriptor(); |
| 536 | |
| 537 | // pin function |
| 538 | // md[4:1]!=0000 |
| 539 | /* initialize GPIO/perihperal function select */ |
| 540 | |
| 541 | pfc_reg_write(PFC_GPSR0, 0x00000000); |
| 542 | |
| 543 | pfc_reg_write(PFC_GPSR1, GPSR1_CANFD_CLK); |
| 544 | |
| 545 | pfc_reg_write(PFC_GPSR2, 0x00000000); |
| 546 | |
| 547 | pfc_reg_write(PFC_GPSR3, 0x00000000); |
| 548 | |
| 549 | pfc_reg_write(PFC_GPSR4, GPSR4_SDA2 |
| 550 | | GPSR4_SCL2); |
| 551 | |
| 552 | pfc_reg_write(PFC_GPSR5, GPSR5_QSPI1_SSL |
| 553 | | GPSR5_QSPI1_IO3 |
| 554 | | GPSR5_QSPI1_IO2 |
| 555 | | GPSR5_QSPI1_MISO_IO1 |
| 556 | | GPSR5_QSPI1_MOSI_IO0 |
| 557 | | GPSR5_QSPI1_SPCLK |
| 558 | | GPSR5_QSPI0_SSL |
| 559 | | GPSR5_QSPI0_IO3 |
| 560 | | GPSR5_QSPI0_IO2 |
| 561 | | GPSR5_QSPI0_MISO_IO1 |
| 562 | | GPSR5_QSPI0_MOSI_IO0 |
| 563 | | GPSR5_QSPI0_SPCLK); |
| 564 | |
| 565 | |
| 566 | /* initialize peripheral function select */ |
| 567 | pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0) |
| 568 | | IPSR_24_FUNC(0) |
| 569 | | IPSR_20_FUNC(0) |
| 570 | | IPSR_16_FUNC(0) |
| 571 | | IPSR_12_FUNC(0) |
| 572 | | IPSR_8_FUNC(0) |
| 573 | | IPSR_4_FUNC(0) |
| 574 | | IPSR_0_FUNC(0)); |
| 575 | |
| 576 | pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(0) |
| 577 | | IPSR_24_FUNC(0) |
| 578 | | IPSR_20_FUNC(0) |
| 579 | | IPSR_16_FUNC(0) |
| 580 | | IPSR_12_FUNC(0) |
| 581 | | IPSR_8_FUNC(0) |
| 582 | | IPSR_4_FUNC(0) |
| 583 | | IPSR_0_FUNC(0)); |
| 584 | |
| 585 | pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(0) |
| 586 | | IPSR_24_FUNC(0) |
| 587 | | IPSR_20_FUNC(0) |
| 588 | | IPSR_16_FUNC(0) |
| 589 | | IPSR_12_FUNC(0) |
| 590 | | IPSR_8_FUNC(0) |
| 591 | | IPSR_4_FUNC(0) |
| 592 | | IPSR_0_FUNC(0)); |
| 593 | |
| 594 | pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(0) |
| 595 | | IPSR_24_FUNC(0) |
| 596 | | IPSR_20_FUNC(0) |
| 597 | | IPSR_16_FUNC(0) |
| 598 | | IPSR_12_FUNC(0) |
| 599 | | IPSR_8_FUNC(0) |
| 600 | | IPSR_4_FUNC(0) |
| 601 | | IPSR_0_FUNC(0)); |
| 602 | |
| 603 | pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(0) |
| 604 | | IPSR_24_FUNC(0) |
| 605 | | IPSR_20_FUNC(0) |
| 606 | | IPSR_16_FUNC(0) |
| 607 | | IPSR_12_FUNC(0) |
| 608 | | IPSR_8_FUNC(0) |
| 609 | | IPSR_4_FUNC(0) |
| 610 | | IPSR_0_FUNC(0)); |
| 611 | |
| 612 | pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(0) |
| 613 | | IPSR_24_FUNC(0) |
| 614 | | IPSR_20_FUNC(0) |
| 615 | | IPSR_16_FUNC(0) |
| 616 | | IPSR_12_FUNC(0) |
| 617 | | IPSR_8_FUNC(0) |
| 618 | | IPSR_4_FUNC(0) |
| 619 | | IPSR_0_FUNC(0)); |
| 620 | |
| 621 | pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(0) |
| 622 | | IPSR_24_FUNC(0) |
| 623 | | IPSR_20_FUNC(0) |
| 624 | | IPSR_16_FUNC(0) |
| 625 | | IPSR_12_FUNC(0) |
| 626 | | IPSR_8_FUNC(0) |
| 627 | | IPSR_4_FUNC(0) |
| 628 | | IPSR_0_FUNC(0)); |
| 629 | |
| 630 | pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0) |
| 631 | | IPSR_24_FUNC(4) |
| 632 | | IPSR_20_FUNC(4) |
| 633 | | IPSR_16_FUNC(4) |
| 634 | | IPSR_12_FUNC(4) |
| 635 | | IPSR_8_FUNC(0) |
| 636 | | IPSR_4_FUNC(0) |
| 637 | | IPSR_0_FUNC(0)); |
| 638 | |
| 639 | pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(0) |
| 640 | | IPSR_24_FUNC(0) |
| 641 | | IPSR_20_FUNC(0) |
| 642 | | IPSR_16_FUNC(4) |
| 643 | | IPSR_12_FUNC(0) |
| 644 | | IPSR_8_FUNC(0) |
| 645 | | IPSR_4_FUNC(0) |
| 646 | | IPSR_0_FUNC(0)); |
| 647 | |
| 648 | /* initialize POC Control */ |
| 649 | |
| Marek Vasut | c73bad9 | 2019-06-17 19:10:05 +0200 | [diff] [blame^] | 650 | pfc_reg_write(PFC_POCCTRL0, IOCTRL30_POC_VI0_DATA5 |
| Valentine Barshak | f218414 | 2018-10-30 02:06:17 +0300 | [diff] [blame] | 651 | | IOCTRL30_POC_VI0_DATA4 |
| 652 | | IOCTRL30_POC_VI0_DATA3 |
| 653 | | IOCTRL30_POC_VI0_DATA2 |
| 654 | | IOCTRL30_POC_VI0_DATA1 |
| 655 | | IOCTRL30_POC_VI0_DATA0 |
| 656 | | IOCTRL30_POC_VI0_VSYNC_N |
| 657 | | IOCTRL30_POC_VI0_HSYNC_N |
| 658 | | IOCTRL30_POC_VI0_CLKENB |
| 659 | | IOCTRL30_POC_VI0_CLK |
| 660 | | IOCTRL30_POC_DU_EXODDF_DU_ODDF_DISP_CDE |
| 661 | | IOCTRL30_POC_DU_EXVSYNC_DU_VSYNC |
| 662 | | IOCTRL30_POC_DU_EXHSYNC_DU_HSYNC |
| 663 | | IOCTRL30_POC_DU_DOTCLKOUT |
| 664 | | IOCTRL30_POC_DU_DB7 |
| 665 | | IOCTRL30_POC_DU_DB6 |
| 666 | | IOCTRL30_POC_DU_DB5 |
| 667 | | IOCTRL30_POC_DU_DB4 |
| 668 | | IOCTRL30_POC_DU_DB3 |
| 669 | | IOCTRL30_POC_DU_DB2 |
| 670 | | IOCTRL30_POC_DU_DG7 |
| 671 | | IOCTRL30_POC_DU_DG6 |
| 672 | | IOCTRL30_POC_DU_DG5 |
| 673 | | IOCTRL30_POC_DU_DG4 |
| 674 | | IOCTRL30_POC_DU_DG3 |
| 675 | | IOCTRL30_POC_DU_DG2 |
| 676 | | IOCTRL30_POC_DU_DR7 |
| 677 | | IOCTRL30_POC_DU_DR6 |
| 678 | | IOCTRL30_POC_DU_DR5 |
| 679 | | IOCTRL30_POC_DU_DR4 |
| 680 | | IOCTRL30_POC_DU_DR3 |
| 681 | | IOCTRL30_POC_DU_DR2); |
| 682 | |
| 683 | pfc_reg_write(PFC_IOCTRL31, IOCTRL31_POC_DUMMY_31 |
| 684 | | IOCTRL31_POC_DUMMY_30 |
| 685 | | IOCTRL31_POC_DUMMY_29 |
| 686 | | IOCTRL31_POC_DUMMY_28 |
| 687 | | IOCTRL31_POC_DUMMY_27 |
| 688 | | IOCTRL31_POC_DUMMY_26 |
| 689 | | IOCTRL31_POC_DUMMY_25 |
| 690 | | IOCTRL31_POC_DUMMY_24 |
| 691 | | IOCTRL31_POC_VI1_FIELD |
| 692 | | IOCTRL31_POC_VI1_DATA11 |
| 693 | | IOCTRL31_POC_VI1_DATA10 |
| 694 | | IOCTRL31_POC_VI1_DATA9 |
| 695 | | IOCTRL31_POC_VI1_DATA8 |
| 696 | | IOCTRL31_POC_VI1_DATA7 |
| 697 | | IOCTRL31_POC_VI1_DATA6 |
| 698 | | IOCTRL31_POC_VI1_DATA5 |
| 699 | | IOCTRL31_POC_VI1_DATA4 |
| 700 | | IOCTRL31_POC_VI1_DATA3 |
| 701 | | IOCTRL31_POC_VI1_DATA2 |
| 702 | | IOCTRL31_POC_VI1_DATA1 |
| 703 | | IOCTRL31_POC_VI1_DATA0 |
| 704 | | IOCTRL31_POC_VI1_VSYNC_N |
| 705 | | IOCTRL31_POC_VI1_HSYNC_N |
| 706 | | IOCTRL31_POC_VI1_CLKENB |
| 707 | | IOCTRL31_POC_VI1_CLK |
| 708 | | IOCTRL31_POC_VI0_FIELD |
| 709 | | IOCTRL31_POC_VI0_DATA11 |
| 710 | | IOCTRL31_POC_VI0_DATA10 |
| 711 | | IOCTRL31_POC_VI0_DATA9 |
| 712 | | IOCTRL31_POC_VI0_DATA8 |
| 713 | | IOCTRL31_POC_VI0_DATA7 |
| 714 | | IOCTRL31_POC_VI0_DATA6); |
| 715 | |
| Marek Vasut | c73bad9 | 2019-06-17 19:10:05 +0200 | [diff] [blame^] | 716 | pfc_reg_write(PFC_POCCTRL1, 0x00000000); |
| Valentine Barshak | f218414 | 2018-10-30 02:06:17 +0300 | [diff] [blame] | 717 | |
| Marek Vasut | c73bad9 | 2019-06-17 19:10:05 +0200 | [diff] [blame^] | 718 | pfc_reg_write(PFC_TDSELCTRL0, 0x00000000); |
| Valentine Barshak | f218414 | 2018-10-30 02:06:17 +0300 | [diff] [blame] | 719 | |
| 720 | /* initialize Pull enable */ |
| 721 | pfc_reg_write(PFC_PUEN0,PUEN0_PUEN_VI0_CLK |
| 722 | | PUEN0_PUEN_TDI |
| 723 | | PUEN0_PUEN_TMS |
| 724 | | PUEN0_PUEN_TCK |
| 725 | | PUEN0_PUEN_TRST_N |
| 726 | | PUEN0_PUEN_IRQ0 |
| 727 | | PUEN0_PUEN_FSCLKST_N |
| 728 | | PUEN0_PUEN_DU_EXHSYNC_DU_HSYNC |
| 729 | | PUEN0_PUEN_DU_DOTCLKOUT |
| 730 | | PUEN0_PUEN_DU_DB7 |
| 731 | | PUEN0_PUEN_DU_DB6 |
| 732 | | PUEN0_PUEN_DU_DB5 |
| 733 | | PUEN0_PUEN_DU_DB4 |
| 734 | | PUEN0_PUEN_DU_DB3 |
| 735 | | PUEN0_PUEN_DU_DB2 |
| 736 | | PUEN0_PUEN_DU_DG7 |
| 737 | | PUEN0_PUEN_DU_DG6 |
| 738 | | PUEN0_PUEN_DU_DG5 |
| 739 | | PUEN0_PUEN_DU_DG4 |
| 740 | | PUEN0_PUEN_DU_DG3 |
| 741 | | PUEN0_PUEN_DU_DG2 |
| 742 | | PUEN0_PUEN_DU_DR7 |
| 743 | | PUEN0_PUEN_DU_DR6 |
| 744 | | PUEN0_PUEN_DU_DR5 |
| 745 | | PUEN0_PUEN_DU_DR4 |
| 746 | | PUEN0_PUEN_DU_DR3 |
| 747 | | PUEN0_PUEN_DU_DR2); |
| 748 | |
| 749 | pfc_reg_write(PFC_PUEN1,PUEN1_PUEN_VI1_DATA11 |
| 750 | | PUEN1_PUEN_VI1_DATA10 |
| 751 | | PUEN1_PUEN_VI1_DATA9 |
| 752 | | PUEN1_PUEN_VI1_DATA8 |
| 753 | | PUEN1_PUEN_VI1_DATA7 |
| 754 | | PUEN1_PUEN_VI1_DATA6 |
| 755 | | PUEN1_PUEN_VI1_DATA5 |
| 756 | | PUEN1_PUEN_VI1_DATA4 |
| 757 | | PUEN1_PUEN_VI1_DATA3 |
| 758 | | PUEN1_PUEN_VI1_DATA2 |
| 759 | | PUEN1_PUEN_VI1_DATA1 |
| 760 | | PUEN1_PUEN_VI1_DATA0 |
| 761 | | PUEN1_PUEN_VI1_VSYNC_N |
| 762 | | PUEN1_PUEN_VI1_HSYNC_N |
| 763 | | PUEN1_PUEN_VI1_CLKENB |
| 764 | | PUEN1_PUEN_VI1_CLK |
| 765 | | PUEN1_PUEN_VI0_DATA11 |
| 766 | | PUEN1_PUEN_VI0_DATA10 |
| 767 | | PUEN1_PUEN_VI0_DATA9 |
| 768 | | PUEN1_PUEN_VI0_DATA8 |
| 769 | | PUEN1_PUEN_VI0_DATA7 |
| 770 | | PUEN1_PUEN_VI0_DATA6 |
| 771 | | PUEN1_PUEN_VI0_DATA5 |
| 772 | | PUEN1_PUEN_VI0_DATA4 |
| 773 | | PUEN1_PUEN_VI0_DATA3 |
| 774 | | PUEN1_PUEN_VI0_DATA2 |
| 775 | | PUEN1_PUEN_VI0_DATA1); |
| 776 | |
| 777 | pfc_reg_write(PFC_PUEN2,PUEN2_PUEN_CANFD_CLK |
| 778 | | PUEN2_PUEN_CANFD1_RX |
| 779 | | PUEN2_PUEN_CANFD1_TX |
| 780 | | PUEN2_PUEN_CANFD0_RX |
| 781 | | PUEN2_PUEN_CANFD0_TX |
| 782 | | PUEN2_PUEN_AVB0_AVTP_CAPTURE |
| 783 | | PUEN2_PUEN_AVB0_AVTP_MATCH |
| 784 | | PUEN2_PUEN_AVB0_LINK |
| 785 | | PUEN2_PUEN_AVB0_PHY_INT |
| 786 | | PUEN2_PUEN_AVB0_MAGIC |
| 787 | | PUEN2_PUEN_AVB0_TXCREFCLK |
| 788 | | PUEN2_PUEN_AVB0_TD3 |
| 789 | | PUEN2_PUEN_AVB0_TD2 |
| 790 | | PUEN2_PUEN_AVB0_TD1 |
| 791 | | PUEN2_PUEN_AVB0_TD0 |
| 792 | | PUEN2_PUEN_AVB0_TXC |
| 793 | | PUEN2_PUEN_AVB0_TX_CTL |
| 794 | | PUEN2_PUEN_AVB0_RD3 |
| 795 | | PUEN2_PUEN_AVB0_RD2 |
| 796 | | PUEN2_PUEN_AVB0_RD1 |
| 797 | | PUEN2_PUEN_AVB0_RD0 |
| 798 | | PUEN2_PUEN_AVB0_RXC |
| 799 | | PUEN2_PUEN_AVB0_RX_CTL |
| 800 | | PUEN2_PUEN_VI1_FIELD); |
| 801 | |
| 802 | pfc_reg_write(PFC_PUEN3,PUEN3_PUEN_DIGRF_CLKOUT |
| 803 | | PUEN3_PUEN_DIGRF_CLKIN); |
| 804 | |
| 805 | /* initialize PUD Control */ |
| 806 | pfc_reg_write(PFC_PUD0,PUD0_PUD_VI0_CLK |
| 807 | | PUD0_PUD_IRQ0 |
| 808 | | PUD0_PUD_FSCLKST_N |
| 809 | | PUD0_PUD_DU_EXODDF_DU_ODDF_DISP_CDE |
| 810 | | PUD0_PUD_DU_EXVSYNC_DU_VSYNC |
| 811 | | PUD0_PUD_DU_EXHSYNC_DU_HSYNC |
| 812 | | PUD0_PUD_DU_DOTCLKOUT |
| 813 | | PUD0_PUD_DU_DB7 |
| 814 | | PUD0_PUD_DU_DB6 |
| 815 | | PUD0_PUD_DU_DB5 |
| 816 | | PUD0_PUD_DU_DB4 |
| 817 | | PUD0_PUD_DU_DB3 |
| 818 | | PUD0_PUD_DU_DB2 |
| 819 | | PUD0_PUD_DU_DG7 |
| 820 | | PUD0_PUD_DU_DG6 |
| 821 | | PUD0_PUD_DU_DG5 |
| 822 | | PUD0_PUD_DU_DG4 |
| 823 | | PUD0_PUD_DU_DG3 |
| 824 | | PUD0_PUD_DU_DG2 |
| 825 | | PUD0_PUD_DU_DR7 |
| 826 | | PUD0_PUD_DU_DR6 |
| 827 | | PUD0_PUD_DU_DR5 |
| 828 | | PUD0_PUD_DU_DR4 |
| 829 | | PUD0_PUD_DU_DR3 |
| 830 | | PUD0_PUD_DU_DR2); |
| 831 | |
| 832 | pfc_reg_write(PFC_PUD1,PUD1_PUD_VI1_DATA11 |
| 833 | | PUD1_PUD_VI1_DATA10 |
| 834 | | PUD1_PUD_VI1_DATA9 |
| 835 | | PUD1_PUD_VI1_DATA8 |
| 836 | | PUD1_PUD_VI1_DATA7 |
| 837 | | PUD1_PUD_VI1_DATA6 |
| 838 | | PUD1_PUD_VI1_DATA5 |
| 839 | | PUD1_PUD_VI1_DATA4 |
| 840 | | PUD1_PUD_VI1_DATA3 |
| 841 | | PUD1_PUD_VI1_DATA2 |
| 842 | | PUD1_PUD_VI1_DATA1 |
| 843 | | PUD1_PUD_VI1_DATA0 |
| 844 | | PUD1_PUD_VI1_VSYNC_N |
| 845 | | PUD1_PUD_VI1_HSYNC_N |
| 846 | | PUD1_PUD_VI1_CLKENB |
| 847 | | PUD1_PUD_VI1_CLK |
| 848 | | PUD1_PUD_VI0_DATA11 |
| 849 | | PUD1_PUD_VI0_DATA10 |
| 850 | | PUD1_PUD_VI0_DATA9 |
| 851 | | PUD1_PUD_VI0_DATA8 |
| 852 | | PUD1_PUD_VI0_DATA7 |
| 853 | | PUD1_PUD_VI0_DATA6 |
| 854 | | PUD1_PUD_VI0_DATA5 |
| 855 | | PUD1_PUD_VI0_DATA4 |
| 856 | | PUD1_PUD_VI0_DATA3 |
| 857 | | PUD1_PUD_VI0_DATA2 |
| 858 | | PUD1_PUD_VI0_DATA1 |
| 859 | | PUD1_PUD_VI0_DATA0 |
| 860 | | PUD1_PUD_VI0_VSYNC_N |
| 861 | | PUD1_PUD_VI0_HSYNC_N |
| 862 | | PUD1_PUD_VI0_CLKENB); |
| 863 | |
| 864 | pfc_reg_write(PFC_PUD2,PUD2_PUD_CANFD_CLK |
| 865 | | PUD2_PUD_CANFD1_RX |
| 866 | | PUD2_PUD_CANFD1_TX |
| 867 | | PUD2_PUD_CANFD0_RX |
| 868 | | PUD2_PUD_CANFD0_TX |
| 869 | | PUD2_PUD_AVB0_AVTP_CAPTURE |
| 870 | | PUD2_PUD_VI1_FIELD); |
| 871 | |
| 872 | pfc_reg_write(PFC_PUD3,PUD3_PUD_DIGRF_CLKOUT |
| 873 | | PUD3_PUD_DIGRF_CLKIN); |
| 874 | |
| 875 | /* initialize Module Select */ |
| 876 | pfc_reg_write(PFC_MOD_SEL0,0x00000000); |
| 877 | |
| 878 | // gpio |
| 879 | /* initialize positive/negative logic select */ |
| 880 | mmio_write_32(GPIO_POSNEG0, 0x00000000U); |
| 881 | mmio_write_32(GPIO_POSNEG1, 0x00000000U); |
| 882 | mmio_write_32(GPIO_POSNEG2, 0x00000000U); |
| 883 | mmio_write_32(GPIO_POSNEG3, 0x00000000U); |
| 884 | mmio_write_32(GPIO_POSNEG4, 0x00000000U); |
| 885 | mmio_write_32(GPIO_POSNEG5, 0x00000000U); |
| 886 | |
| 887 | /* initialize general IO/interrupt switching */ |
| 888 | mmio_write_32(GPIO_IOINTSEL0, 0x00000000U); |
| 889 | mmio_write_32(GPIO_IOINTSEL1, 0x00000000U); |
| 890 | mmio_write_32(GPIO_IOINTSEL2, 0x00000000U); |
| 891 | mmio_write_32(GPIO_IOINTSEL3, 0x00000000U); |
| 892 | mmio_write_32(GPIO_IOINTSEL4, 0x00000000U); |
| 893 | mmio_write_32(GPIO_IOINTSEL5, 0x00000000U); |
| 894 | |
| 895 | /* initialize general output register */ |
| 896 | mmio_write_32(GPIO_OUTDT0, 0x00000000U); |
| 897 | mmio_write_32(GPIO_OUTDT1, 0x00000000U); |
| 898 | mmio_write_32(GPIO_OUTDT2, 0x00000000U); |
| 899 | mmio_write_32(GPIO_OUTDT3, 0x00000000U); |
| 900 | mmio_write_32(GPIO_OUTDT4, 0x00000000U); |
| 901 | mmio_write_32(GPIO_OUTDT5, 0x00000000U); |
| 902 | |
| 903 | /* initialize general input/output switching */ |
| 904 | mmio_write_32(GPIO_INOUTSEL0, 0x00000000U); |
| 905 | mmio_write_32(GPIO_INOUTSEL1, 0x00000000U); |
| 906 | mmio_write_32(GPIO_INOUTSEL2, 0x00000000U); |
| 907 | mmio_write_32(GPIO_INOUTSEL3, 0x00000000U); |
| 908 | mmio_write_32(GPIO_INOUTSEL4, 0x00000000U); |
| 909 | mmio_write_32(GPIO_INOUTSEL5, 0x00000000U); |
| 910 | } |