| Aditya Angadi | d61740b | 2020-11-19 18:05:33 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef PLATFORM_DEF_H |
| 8 | #define PLATFORM_DEF_H |
| 9 | |
| 10 | #include <lib/utils_def.h> |
| 11 | |
| 12 | #include <sgi_soc_platform_def_v2.h> |
| 13 | |
| Aditya Angadi | f894b9a | 2021-03-20 12:15:04 +0530 | [diff] [blame] | 14 | #if (CSS_SGI_PLATFORM_VARIANT == 1) |
| 15 | #define PLAT_ARM_CLUSTER_COUNT U(8) |
| 16 | #else |
| Aditya Angadi | d61740b | 2020-11-19 18:05:33 +0530 | [diff] [blame] | 17 | #define PLAT_ARM_CLUSTER_COUNT U(16) |
| Aditya Angadi | f894b9a | 2021-03-20 12:15:04 +0530 | [diff] [blame] | 18 | #endif |
| 19 | |
| Aditya Angadi | d61740b | 2020-11-19 18:05:33 +0530 | [diff] [blame] | 20 | #define CSS_SGI_MAX_CPUS_PER_CLUSTER U(1) |
| 21 | #define CSS_SGI_MAX_PE_PER_CPU U(1) |
| 22 | |
| 23 | #define PLAT_CSS_MHU_BASE UL(0x2A920000) |
| 24 | #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE |
| 25 | |
| 26 | #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 |
| 27 | #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 |
| 28 | |
| 29 | /* TZC Related Constants */ |
| Vijayenthiran Subramaniam | 478ccb3 | 2021-02-04 18:15:40 +0530 | [diff] [blame] | 30 | #define PLAT_ARM_TZC_BASE UL(0x10720000) |
| Aditya Angadi | d61740b | 2020-11-19 18:05:33 +0530 | [diff] [blame] | 31 | #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) |
| 32 | |
| 33 | #define TZC400_OFFSET UL(0x1000000) |
| Aditya Angadi | f894b9a | 2021-03-20 12:15:04 +0530 | [diff] [blame] | 34 | |
| 35 | #if (CSS_SGI_PLATFORM_VARIANT == 1) |
| 36 | #define TZC400_COUNT U(2) |
| 37 | #else |
| Aditya Angadi | d61740b | 2020-11-19 18:05:33 +0530 | [diff] [blame] | 38 | #define TZC400_COUNT U(8) |
| Aditya Angadi | f894b9a | 2021-03-20 12:15:04 +0530 | [diff] [blame] | 39 | #endif |
| Aditya Angadi | d61740b | 2020-11-19 18:05:33 +0530 | [diff] [blame] | 40 | |
| 41 | #define TZC400_BASE(n) (PLAT_ARM_TZC_BASE + \ |
| 42 | (n * TZC400_OFFSET)) |
| 43 | |
| 44 | #define TZC_NSAID_ALL_AP U(0) |
| 45 | #define TZC_NSAID_PCI U(1) |
| 46 | #define TZC_NSAID_HDLCD0 U(2) |
| 47 | #define TZC_NSAID_CLCD U(7) |
| 48 | #define TZC_NSAID_AP U(9) |
| 49 | #define TZC_NSAID_VIRTIO U(15) |
| 50 | |
| 51 | #define PLAT_ARM_TZC_NS_DEV_ACCESS \ |
| 52 | (TZC_REGION_ACCESS_RDWR(TZC_NSAID_ALL_AP)) | \ |
| 53 | (TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD0)) | \ |
| 54 | (TZC_REGION_ACCESS_RDWR(TZC_NSAID_PCI)) | \ |
| 55 | (TZC_REGION_ACCESS_RDWR(TZC_NSAID_AP)) | \ |
| 56 | (TZC_REGION_ACCESS_RDWR(TZC_NSAID_CLCD)) | \ |
| 57 | (TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIRTIO)) |
| 58 | |
| 59 | /* |
| 60 | * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes |
| 61 | */ |
| 62 | #ifdef __aarch64__ |
| 63 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 42) |
| 64 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 42) |
| 65 | #else |
| 66 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) |
| 67 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) |
| 68 | #endif |
| 69 | |
| 70 | /* GIC related constants */ |
| 71 | #define PLAT_ARM_GICD_BASE UL(0x30000000) |
| 72 | #define PLAT_ARM_GICC_BASE UL(0x2C000000) |
| Aditya Angadi | f894b9a | 2021-03-20 12:15:04 +0530 | [diff] [blame] | 73 | |
| 74 | #if (CSS_SGI_PLATFORM_VARIANT == 1) |
| 75 | #define PLAT_ARM_GICR_BASE UL(0x30100000) |
| 76 | #else |
| Vijayenthiran Subramaniam | 777a9ff | 2020-12-15 20:07:43 +0530 | [diff] [blame] | 77 | #define PLAT_ARM_GICR_BASE UL(0x301C0000) |
| Aditya Angadi | f894b9a | 2021-03-20 12:15:04 +0530 | [diff] [blame] | 78 | #endif |
| Aditya Angadi | d61740b | 2020-11-19 18:05:33 +0530 | [diff] [blame] | 79 | |
| 80 | #endif /* PLATFORM_DEF_H */ |