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Yatharth Kocharb1c2fe02015-10-14 15:27:24 +01001/*
Masahiro Yamada0b67e562020-03-09 17:39:48 +09002 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +01005 */
6
7#include <platform_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008
Masahiro Yamada0b67e562020-03-09 17:39:48 +09009#include <common/bl_common.ld.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <lib/xlat_tables/xlat_tables_defs.h>
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +010011
12OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
13OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
14ENTRY(bl2u_entrypoint)
15
16MEMORY {
17 RAM (rwx): ORIGIN = BL2U_BASE, LENGTH = BL2U_LIMIT - BL2U_BASE
18}
19
20
21SECTIONS
22{
23 . = BL2U_BASE;
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +000024 ASSERT(. == ALIGN(PAGE_SIZE),
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +010025 "BL2U_BASE address is not aligned on a page boundary.")
26
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010027#if SEPARATE_CODE_AND_RODATA
28 .text . : {
29 __TEXT_START__ = .;
30 *bl2u_entrypoint.o(.text*)
Samuel Holland23f5e542019-10-20 16:11:25 -050031 *(SORT_BY_ALIGNMENT(.text*))
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010032 *(.vectors)
Roberto Vargasd93fde32018-04-11 11:53:31 +010033 . = ALIGN(PAGE_SIZE);
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010034 __TEXT_END__ = .;
35 } >RAM
36
Roberto Vargas1d04c632018-05-10 11:01:16 +010037 /* .ARM.extab and .ARM.exidx are only added because Clang need them */
38 .ARM.extab . : {
39 *(.ARM.extab* .gnu.linkonce.armextab.*)
40 } >RAM
41
42 .ARM.exidx . : {
43 *(.ARM.exidx* .gnu.linkonce.armexidx.*)
44 } >RAM
45
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010046 .rodata . : {
47 __RODATA_START__ = .;
Samuel Holland23f5e542019-10-20 16:11:25 -050048 *(SORT_BY_ALIGNMENT(.rodata*))
Masahiro Yamada583f8dd2020-03-26 10:57:12 +090049
50 RODATA_COMMON
51
Roberto Vargasd93fde32018-04-11 11:53:31 +010052 . = ALIGN(PAGE_SIZE);
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010053 __RODATA_END__ = .;
54 } >RAM
55#else
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +010056 ro . : {
57 __RO_START__ = .;
58 *bl2u_entrypoint.o(.text*)
Samuel Holland23f5e542019-10-20 16:11:25 -050059 *(SORT_BY_ALIGNMENT(.text*))
60 *(SORT_BY_ALIGNMENT(.rodata*))
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +010061
Masahiro Yamada583f8dd2020-03-26 10:57:12 +090062 RODATA_COMMON
63
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +010064 *(.vectors)
65 __RO_END_UNALIGNED__ = .;
66 /*
67 * Memory page(s) mapped to this section will be marked as
68 * read-only, executable. No RW data from the next section must
69 * creep in. Ensure the rest of the current memory page is unused.
70 */
Roberto Vargasd93fde32018-04-11 11:53:31 +010071 . = ALIGN(PAGE_SIZE);
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +010072 __RO_END__ = .;
73 } >RAM
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010074#endif
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +010075
76 /*
77 * Define a linker symbol to mark start of the RW memory area for this
78 * image.
79 */
80 __RW_START__ = . ;
81
Masahiro Yamadac5864d82020-04-22 10:50:12 +090082 DATA_SECTION >RAM
Masahiro Yamada403990e2020-04-07 13:04:24 +090083 STACK_SECTION >RAM
Masahiro Yamadadd053b62020-03-26 13:16:33 +090084 BSS_SECTION >RAM
Masahiro Yamada0b67e562020-03-09 17:39:48 +090085 XLAT_TABLE_SECTION >RAM
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +010086
87#if USE_COHERENT_MEM
88 /*
89 * The base address of the coherent memory section must be page-aligned (4K)
90 * to guarantee that the coherent data are stored on their own pages and
91 * are not mixed with normal data. This is required to set up the correct
92 * memory attributes for the coherent data page tables.
93 */
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +000094 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +010095 __COHERENT_RAM_START__ = .;
96 *(tzfw_coherent_mem)
97 __COHERENT_RAM_END_UNALIGNED__ = .;
98 /*
99 * Memory page(s) mapped to this section will be marked
100 * as device memory. No other unexpected data must creep in.
101 * Ensure the rest of the current memory page is unused.
102 */
Roberto Vargasd93fde32018-04-11 11:53:31 +0100103 . = ALIGN(PAGE_SIZE);
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +0100104 __COHERENT_RAM_END__ = .;
105 } >RAM
106#endif
107
108 /*
109 * Define a linker symbol to mark end of the RW memory area for this
110 * image.
111 */
112 __RW_END__ = .;
113 __BL2U_END__ = .;
114
115 __BSS_SIZE__ = SIZEOF(.bss);
116
117 ASSERT(. <= BL2U_LIMIT, "BL2U image has exceeded its limit.")
118}