blob: 7f9806001f80015ce9101b631104bf1e4bd1897a [file] [log] [blame]
Nariman Poushinc703f902018-03-07 10:29:57 +00001/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <debug.h>
8#include <plat_arm.h>
9#include <sgm_variant.h>
10#include <soc_css.h>
11#include <tzc_dmc500.h>
12
13/* Is populated with the DMC-500 controllers base addresses */
14static tzc_dmc500_driver_data_t plat_driver_data;
15
16void plat_sgm_dp_security_setup(void)
17{
18 unsigned int nprot_nsaid;
19
20 /*
21 * At reset the Mali display processors start with NSAIDs set to zero
22 * so the firmware must set them up to the expected values for ARM sgm
23 * platforms.
24 */
25
26 nprot_nsaid = mmio_read_32(MALI_DP_BASE + DP_NPROT_NSAID_OFFSET);
27 nprot_nsaid &= ~((0xF << W_NPROT_NSAID_SHIFT) |
28 (0xF << LS_NPORT_NSAID_SHIFT));
29 nprot_nsaid |= ((TZC_NSAID_DISP1 << W_NPROT_NSAID_SHIFT) |
30 (TZC_NSAID_DISP0 << LS_NPORT_NSAID_SHIFT));
31 mmio_write_32(MALI_DP_BASE + DP_NPROT_NSAID_OFFSET, nprot_nsaid);
32}
33
34void plat_arm_security_setup(void)
35{
36 unsigned int i;
37 unsigned int part_num = GET_PLAT_PART_NUM;
38
39 INFO("part_num: 0x%x\n", part_num);
40
41 /*
42 * Initialise plat_driver_data with platform specific DMC_BASE
43 * addresses
44 */
45 switch (part_num) {
46 case SGM775_SSC_VER_PART_NUM:
47 for (i = 0; i < SGM775_DMC_COUNT; i++)
48 plat_driver_data.dmc_base[i] = PLAT_ARM_TZC_BASE
49 + SGM_DMC_SIZE * i;
50 plat_driver_data.dmc_count = SGM775_DMC_COUNT;
51 break;
52 default:
53 /* Unexpected platform */
54 ERROR("Unexpected platform\n");
55 panic();
56 }
57 /* Initialize the TrustZone Controller in DMC-500 */
58 arm_tzc_dmc500_setup(&plat_driver_data, NULL);
59
60 /* Do DP NSAID setup */
61 plat_sgm_dp_security_setup();
62 /* Do ARM CSS SoC security setup */
63 soc_css_security_setup();
64}