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developer550bf5e2016-07-11 16:05:23 +08001/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __PLATFORM_DEF_H__
32#define __PLATFORM_DEF_H__
33
34#define PLAT_PRIMARY_CPU 0x0
35
36/* Special value used to verify platform parameters from BL2 to BL3-1 */
37#define MT_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
38
39#define IO_PHYS (0x10000000)
40#define INFRACFG_AO_BASE (IO_PHYS + 0x1000)
41#define MCUCFG_BASE (IO_PHYS + 0x200000)
42#define PERI_BASE (IO_PHYS + 0x1000000)
43
44
45#define GPIO_BASE (IO_PHYS + 0x370000)
46#define SPM_BASE (IO_PHYS + 0x6000)
47#define RGU_BASE (MCUCFG_BASE + 0x11000)
48#define PMIC_WRAP_BASE (IO_PHYS + 0x10000)
49
50#define TRNG_base (MCUCFG_BASE + 0x230000)
51#define MT_GIC_BASE (0x10220000)
52#define MCU_SYS_SIZE (0x700000)
53#define PLAT_MT_CCI_BASE (IO_PHYS + 0x390000)
54
55/* Aggregate of all devices in the first GB */
56#define MTK_DEV_RNG0_BASE IO_PHYS
57#define MTK_DEV_RNG0_SIZE 0x400000
58#define MTK_DEV_RNG1_BASE (PERI_BASE)
59#define MTK_DEV_RNG1_SIZE 0x4000000
60
61/*******************************************************************************
62 * UART related constants
63 ******************************************************************************/
64#define UART0_BASE (PERI_BASE + 0x2000)
65
66#define UART_BAUDRATE (921600)
67#define UART_CLOCK (26000000)
68
69/*******************************************************************************
70 * System counter frequency related constants
71 ******************************************************************************/
72#define SYS_COUNTER_FREQ_IN_TICKS 13000000
73#define SYS_COUNTER_FREQ_IN_MHZ (SYS_COUNTER_FREQ_IN_TICKS/1000000)
74
75/*******************************************************************************
76 * GIC-400 & interrupt handling related constants
77 ******************************************************************************/
78
79/* Base MTK_platform compatible GIC memory map */
80#define BASE_GICD_BASE (MT_GIC_BASE+0x1000)
81#define BASE_GICC_BASE (MT_GIC_BASE + 0x2000)
82#define BASE_GICR_BASE (MT_GIC_BASE + 0x200000)
83#define BASE_GICH_BASE (MT_GIC_BASE + 0x4000)
84#define BASE_GICV_BASE (MT_GIC_BASE + 0x6000)
85
86#define INT_POL_CTL0 0x10200620
87#define GIC_PRIVATE_SIGNALS (32)
88
89/*******************************************************************************
90 * CCI-400 related constants
91 ******************************************************************************/
92#define PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX 4
93#define PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX 3
94
95/*******************************************************************************
96 * WDT Registers
97 ******************************************************************************/
98#define MTK_WDT_BASE (RGU_BASE)
99#define MTK_WDT_SIZE (0x1000)
100#define MTK_WDT_MODE (MTK_WDT_BASE+0x0000)
101#define MTK_WDT_LENGTH (MTK_WDT_BASE+0x0004)
102#define MTK_WDT_RESTART (MTK_WDT_BASE+0x0008)
103#define MTK_WDT_STATUS (MTK_WDT_BASE+0x000C)
104#define MTK_WDT_INTERVAL (MTK_WDT_BASE+0x0010)
105#define MTK_WDT_SWRST (MTK_WDT_BASE+0x0014)
106#define MTK_WDT_SWSYSRST (MTK_WDT_BASE+0x0018)
107#define MTK_WDT_NONRST_REG (MTK_WDT_BASE+0x0020)
108#define MTK_WDT_NONRST_REG2 (MTK_WDT_BASE+0x0024)
109#define MTK_WDT_REQ_MODE (MTK_WDT_BASE+0x0030)
110#define MTK_WDT_REQ_IRQ_EN (MTK_WDT_BASE+0x0034)
111#define MTK_WDT_DEBUG_CTL (MTK_WDT_BASE+0x0040)
112
113/*WDT_STATUS*/
114#define MTK_WDT_STATUS_HWWDT_RST (0x80000000)
115#define MTK_WDT_STATUS_SWWDT_RST (0x40000000)
116#define MTK_WDT_STATUS_IRQWDT_RST (0x20000000)
117#define MTK_WDT_STATUS_DEBUGWDT_RST (0x00080000)
118#define MTK_WDT_STATUS_SPMWDT_RST (0x0002)
119#define MTK_WDT_STATUS_SPM_THERMAL_RST (0x0001)
120#define MTK_WDT_STATUS_THERMAL_DIRECT_RST (1<<18)
121#define MTK_WDT_STATUS_SECURITY_RST (1<<28)
122
123#define MTK_WDT_MODE_DUAL_MODE 0x0040
124#define MTK_WDT_MODE_IRQ 0x0008
125#define MTK_WDT_MODE_KEY 0x22000000
126#define MTK_WDT_MODE_EXTEN 0x0004
127#define MTK_WDT_SWRST_KEY 0x1209
128#define MTK_WDT_RESTART_KEY (0x1971)
129
130/* FIQ platform related define */
131#define MT_IRQ_SEC_SGI_0 8
132#define MT_IRQ_SEC_SGI_1 9
133#define MT_IRQ_SEC_SGI_2 10
134#define MT_IRQ_SEC_SGI_3 11
135#define MT_IRQ_SEC_SGI_4 12
136#define MT_IRQ_SEC_SGI_5 13
137#define MT_IRQ_SEC_SGI_6 14
138#define MT_IRQ_SEC_SGI_7 15
139
140#define FIQ_SMP_CALL_SGI MT_IRQ_SEC_SGI_5
141
142#define PLAT_ARM_G0_IRQS FIQ_SMP_CALL_SGI
143
144#define DEBUG_XLAT_TABLE 0
145
146/*******************************************************************************
147 * Platform binary types for linking
148 ******************************************************************************/
149#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
150#define PLATFORM_LINKER_ARCH aarch64
151
152/*******************************************************************************
153 * Generic platform constants
154 ******************************************************************************/
155
156/* Size of cacheable stacks */
157#if DEBUG_XLAT_TABLE
158#define PLATFORM_STACK_SIZE 0x800
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900159#elif defined(IMAGE_BL1)
developer550bf5e2016-07-11 16:05:23 +0800160#define PLATFORM_STACK_SIZE 0x440
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900161#elif defined(IMAGE_BL2)
developer550bf5e2016-07-11 16:05:23 +0800162#define PLATFORM_STACK_SIZE 0x400
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900163#elif defined(IMAGE_BL31)
developer550bf5e2016-07-11 16:05:23 +0800164#define PLATFORM_STACK_SIZE 0x800
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900165#elif defined(IMAGE_BL32)
developer550bf5e2016-07-11 16:05:23 +0800166#define PLATFORM_STACK_SIZE 0x440
167#endif
168
169#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
170#if ENABLE_PLAT_COMPAT
171#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2
172#else
173#define PLAT_MAX_PWR_LVL 2 /* MPIDR_AFFLVL2 */
174#endif
175
176#define PLATFORM_CACHE_LINE_SIZE 64
177#define PLATFORM_SYSTEM_COUNT 1
178#define PLATFORM_CLUSTER_COUNT 2
179#define PLATFORM_CLUSTER0_CORE_COUNT 4
180#define PLATFORM_CLUSTER1_CORE_COUNT 4
181#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \
182 PLATFORM_CLUSTER0_CORE_COUNT)
183#define PLATFORM_MAX_CPUS_PER_CLUSTER 4
184#define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \
185 PLATFORM_CLUSTER_COUNT + \
186 PLATFORM_CORE_COUNT)
187
188/*******************************************************************************
189 * Platform memory map related constants
190 ******************************************************************************/
191/* ATF Argument */
192#define ATF_ARG_SIZE (0x800)
193
194/* TF txet, ro, rw, internal SRAM, Size: release: 80KB, debug: 92KB */
195#define TZRAM_BASE (0x110000)
196#if DEBUG
197#define TZRAM_SIZE (0x1C400)
198#else
199#define TZRAM_SIZE (0x1C400)
200#endif
201#define TZRAM2_BASE 0x00100000
202#define TZRAM2_SIZE 0xDC00
203#define TZRAM2_LIMIT (TZRAM2_BASE + TZRAM2_SIZE)
204
205#define RAM_CONSOLE_BASE 0x0012D000
206#define RAM_CONSOLE_SIZE 0x00001000
207/*******************************************************************************
208 * BL31 specific defines.
209 ******************************************************************************/
210/*
211 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if
212 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a
213 * little space for growth.
214 */
215#define BL31_BASE (TZRAM_BASE + 0x1000)
216#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
217#define BSS1_STACK_LIMIT (TZRAM_BASE + TZRAM_SIZE)
218#define BL31_TZRAM_SIZE (TZRAM_SIZE - ATF_ARG_SIZE)
219
220/*******************************************************************************
221 * Platform specific page table and MMU setup constants
222 ******************************************************************************/
223#define ADDR_SPACE_SIZE (1ull << 32)
224#define MAX_XLAT_TABLES 7
225#define MAX_MMAP_REGIONS 16
226
227
228/*******************************************************************************
229 * CCI-400 related constants
230 ******************************************************************************/
231#define CCI400_BASE 0x10390000
232#define CCI400_SL_IFACE_CLUSTER0 4
233#define CCI400_SL_IFACE_CLUSTER1 3
234#define CCI400_SL_IFACE_INDEX(mpidr) (mpidr & MPIDR_CLUSTER_MASK ? \
235 CCI400_SL_IFACE_CLUSTER1 : \
236 CCI400_SL_IFACE_CLUSTER0)
237#define CCI_SEC_ACCESS_OFFSET (0x8)
238
239
240/*******************************************************************************
241 * Declarations and constants to access the mailboxes safely. Each mailbox is
242 * aligned on the biggest cache line size in the platform. This is known only
243 * to the platform as it might have a combination of integrated and external
244 * caches. Such alignment ensures that two maiboxes do not sit on the same cache
245 * line at any cache level. They could belong to different cpus/clusters &
246 * get written while being protected by different locks causing corruption of
247 * a valid mailbox address.
248 ******************************************************************************/
249#define CACHE_WRITEBACK_SHIFT 6
250#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
251
252#define BL32_BASE (0x0)
253
254/*
255 * Load address of BL3-3 for this platform port
256 */
257#define LK_SIZE_LIMIT (0x100000)
258#define PLAT_MTK_NS_IMAGE_OFFSET (0x41E00000)
259/* 16KB */
260#define ATF_AEE_BUFFER_SIZE (0x4000)
261#define PAGE_SIZE_2MB_MASK (PAGE_SIZE_2MB - 1)
262#define IS_PAGE_2MB_ALIGNED(addr) (((addr) & PAGE_SIZE_2MB_MASK) == 0)
263#define PAGE_SIZE_2MB (1 << PAGE_SIZE_2MB_SHIFT)
264#define PAGE_SIZE_2MB_SHIFT TWO_MB_SHIFT
265
266#endif /* __PLATFORM_DEF_H__ */