Biju Das | 2161542 | 2020-11-09 09:38:51 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <stdint.h> |
| 8 | |
| 9 | #include <common/debug.h> |
| 10 | #include <lib/mmio.h> |
| 11 | |
| 12 | #include "../qos_common.h" |
| 13 | #include "qos_init_g2m_v10.h" |
| 14 | #include "qos_init_g2m_v10_mstat.h" |
| 15 | #include "qos_reg.h" |
| 16 | |
| 17 | #define RCAR_QOS_VERSION "rev.0.19" |
| 18 | |
| 19 | static const struct rcar_gen3_dbsc_qos_settings g2m_v10_qos[] = { |
| 20 | /* BUFCAM settings */ |
| 21 | /* DBSC_DBCAM0CNF0 not set */ |
| 22 | { DBSC_DBCAM0CNF1, 0x00043218U }, |
| 23 | { DBSC_DBCAM0CNF2, 0x000000F4U }, |
| 24 | { DBSC_DBCAM0CNF3, 0x00000000U }, |
| 25 | { DBSC_DBSCHCNT0, 0x080F0037U }, |
| 26 | /* DBSC_DBSCHCNT1 not set */ |
| 27 | { DBSC_DBSCHSZ0, 0x00000001U }, |
| 28 | { DBSC_DBSCHRW0, 0x22421111U }, |
| 29 | |
| 30 | /* DDR3 */ |
| 31 | { DBSC_SCFCTST2, 0x012F1123U }, |
| 32 | |
| 33 | /* QoS Settings */ |
| 34 | { DBSC_DBSCHQOS00, 0x00000F00U }, |
| 35 | { DBSC_DBSCHQOS01, 0x00000B00U }, |
| 36 | { DBSC_DBSCHQOS02, 0x00000000U }, |
| 37 | { DBSC_DBSCHQOS03, 0x00000000U }, |
| 38 | { DBSC_DBSCHQOS40, 0x00000300U }, |
| 39 | { DBSC_DBSCHQOS41, 0x000002F0U }, |
| 40 | { DBSC_DBSCHQOS42, 0x00000200U }, |
| 41 | { DBSC_DBSCHQOS43, 0x00000100U }, |
| 42 | { DBSC_DBSCHQOS90, 0x00000300U }, |
| 43 | { DBSC_DBSCHQOS91, 0x000002F0U }, |
| 44 | { DBSC_DBSCHQOS92, 0x00000200U }, |
| 45 | { DBSC_DBSCHQOS93, 0x00000100U }, |
| 46 | { DBSC_DBSCHQOS130, 0x00000100U }, |
| 47 | { DBSC_DBSCHQOS131, 0x000000F0U }, |
| 48 | { DBSC_DBSCHQOS132, 0x000000A0U }, |
| 49 | { DBSC_DBSCHQOS133, 0x00000040U }, |
| 50 | { DBSC_DBSCHQOS140, 0x000000C0U }, |
| 51 | { DBSC_DBSCHQOS141, 0x000000B0U }, |
| 52 | { DBSC_DBSCHQOS142, 0x00000080U }, |
| 53 | { DBSC_DBSCHQOS143, 0x00000040U }, |
| 54 | { DBSC_DBSCHQOS150, 0x00000040U }, |
| 55 | { DBSC_DBSCHQOS151, 0x00000030U }, |
| 56 | { DBSC_DBSCHQOS152, 0x00000020U }, |
| 57 | { DBSC_DBSCHQOS153, 0x00000010U }, |
| 58 | }; |
| 59 | |
| 60 | void qos_init_g2m_v10(void) |
| 61 | { |
| 62 | rzg_qos_dbsc_setting(g2m_v10_qos, ARRAY_SIZE(g2m_v10_qos), false); |
| 63 | |
| 64 | /* DRAM split address mapping */ |
| 65 | #if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH |
| 66 | #if RCAR_LSI == RZ_G2M |
| 67 | #error "Don't set DRAM Split 4ch(G2M)" |
| 68 | #else /* RCAR_LSI == RZ_G2M */ |
| 69 | ERROR("DRAM Split 4ch not supported.(G2M)"); |
| 70 | panic(); |
| 71 | #endif /* RCAR_LSI == RZ_G2M */ |
| 72 | #elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH) || \ |
| 73 | (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO) |
| 74 | NOTICE("BL2: DRAM Split is 2ch\n"); |
| 75 | mmio_write_32(AXI_ADSPLCR0, 0x00000000U); |
| 76 | mmio_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT | |
| 77 | ADSPLCR0_SPLITSEL(0xFFU) | ADSPLCR0_AREA(0x1CU) | |
| 78 | ADSPLCR0_SWP); |
| 79 | mmio_write_32(AXI_ADSPLCR2, 0x089A0000U); |
| 80 | mmio_write_32(AXI_ADSPLCR3, 0x00000000U); |
| 81 | #else /* RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH */ |
| 82 | NOTICE("BL2: DRAM Split is OFF\n"); |
| 83 | #endif /* RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH */ |
| 84 | |
| 85 | #if !(RCAR_QOS_TYPE == RCAR_QOS_NONE) |
| 86 | #if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT |
| 87 | NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION); |
| 88 | #endif |
| 89 | |
| 90 | /* Resource Alloc setting */ |
| 91 | mmio_write_32(QOSCTRL_RAS, 0x00000028U); |
| 92 | mmio_write_32(QOSCTRL_FIXTH, 0x000F0005U); |
| 93 | mmio_write_32(QOSCTRL_REGGD, 0x00000000U); |
| 94 | mmio_write_64(QOSCTRL_DANN, 0x0101010102020201UL); |
| 95 | mmio_write_32(QOSCTRL_DANT, 0x00100804U); |
| 96 | mmio_write_32(QOSCTRL_EC, 0x00000000U); |
| 97 | mmio_write_64(QOSCTRL_EMS, 0x0000000000000000UL); |
| 98 | mmio_write_32(QOSCTRL_FSS, 0x000003e8U); |
| 99 | mmio_write_32(QOSCTRL_INSFC, 0xC7840001U); |
| 100 | mmio_write_32(QOSCTRL_BERR, 0x00000000U); |
| 101 | mmio_write_32(QOSCTRL_RACNT0, 0x00000000U); |
| 102 | |
| 103 | /* QOSBW setting */ |
| 104 | mmio_write_32(QOSCTRL_SL_INIT, SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | |
| 105 | SL_INIT_SSLOTCLK); |
| 106 | mmio_write_32(QOSCTRL_REF_ARS, 0x00330000U); |
| 107 | |
| 108 | /* QOSBW SRAM setting */ |
| 109 | uint32_t i; |
| 110 | |
| 111 | for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { |
| 112 | mmio_write_64(QOSBW_FIX_QOS_BANK0 + i * 8U, mstat_fix[i]); |
| 113 | mmio_write_64(QOSBW_FIX_QOS_BANK1 + i * 8U, mstat_fix[i]); |
| 114 | } |
| 115 | for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { |
| 116 | mmio_write_64(QOSBW_BE_QOS_BANK0 + i * 8U, mstat_be[i]); |
| 117 | mmio_write_64(QOSBW_BE_QOS_BANK1 + i * 8U, mstat_be[i]); |
| 118 | } |
| 119 | |
| 120 | /* 3DG bus Leaf setting */ |
| 121 | mmio_write_32(0xFD820808U, 0x00001234U); |
| 122 | mmio_write_32(0xFD820800U, 0x00000006U); |
| 123 | mmio_write_32(0xFD821800U, 0x00000006U); |
| 124 | mmio_write_32(0xFD822800U, 0x00000006U); |
| 125 | mmio_write_32(0xFD823800U, 0x00000006U); |
| 126 | mmio_write_32(0xFD824800U, 0x00000006U); |
| 127 | mmio_write_32(0xFD825800U, 0x00000006U); |
| 128 | mmio_write_32(0xFD826800U, 0x00000006U); |
| 129 | mmio_write_32(0xFD827800U, 0x00000006U); |
| 130 | |
| 131 | /* RT bus Leaf setting */ |
| 132 | mmio_write_32(0xFFC50800U, 0x00000000U); |
| 133 | mmio_write_32(0xFFC51800U, 0x00000000U); |
| 134 | |
| 135 | /* Resource Alloc start */ |
| 136 | mmio_write_32(QOSCTRL_RAEN, 0x00000001U); |
| 137 | |
| 138 | /* QOSBW start */ |
| 139 | mmio_write_32(QOSCTRL_STATQC, 0x00000001U); |
| 140 | #else /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */ |
| 141 | NOTICE("BL2: QoS is None\n"); |
| 142 | |
| 143 | /* Resource Alloc setting */ |
| 144 | mmio_write_32(QOSCTRL_EC, 0x00000000U); |
| 145 | /* Resource Alloc start */ |
| 146 | mmio_write_32(QOSCTRL_RAEN, 0x00000001U); |
| 147 | #endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */ |
| 148 | } |