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Sandrine Bailleux798140d2014-07-17 16:06:39 +01001/*
Dan Handley7bef8002015-03-19 19:22:44 +00002 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
Sandrine Bailleux798140d2014-07-17 16:06:39 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
32#include <asm_macros.S>
33#include <bl_common.h>
Sandrine Bailleux9d548a22015-11-18 11:10:30 +000034#include <cortex_a53.h>
Sandrine Bailleux798140d2014-07-17 16:06:39 +010035#include <cortex_a57.h>
Sandrine Bailleux29a7a032015-11-18 11:59:35 +000036#include <cortex_a72.h>
Dan Handley7bef8002015-03-19 19:22:44 +000037#include <v2m_def.h>
Sandrine Bailleux798140d2014-07-17 16:06:39 +010038#include "../juno_def.h"
39
Sandrine Bailleux798140d2014-07-17 16:06:39 +010040
Dan Handley7bef8002015-03-19 19:22:44 +000041 .globl plat_reset_handler
David Wang323ebe82015-10-22 13:30:50 +080042 .globl plat_arm_calc_core_pos
Sandrine Bailleux798140d2014-07-17 16:06:39 +010043
Sandrine Bailleux9d548a22015-11-18 11:10:30 +000044#define JUNO_REVISION(rev) REV_JUNO_R##rev
45#define JUNO_HANDLER(rev) plat_reset_handler_juno_r##rev
46#define JUMP_TO_HANDLER_IF_JUNO_R(revision) \
47 jump_to_handler JUNO_REVISION(revision), JUNO_HANDLER(revision)
48
Sandrine Bailleuxfd8f8982015-02-04 14:06:10 +000049 /* --------------------------------------------------------------------
Sandrine Bailleux9d548a22015-11-18 11:10:30 +000050 * Helper macro to jump to the given handler if the board revision
51 * matches.
52 * Expects the Juno board revision in x0.
53 * --------------------------------------------------------------------
54 */
55 .macro jump_to_handler _revision, _handler
56 cmp x0, #\_revision
57 b.eq \_handler
58 .endm
59
60 /* --------------------------------------------------------------------
61 * Helper macro that reads the part number of the current CPU and jumps
62 * to the given label if it matches the CPU MIDR provided.
63 *
64 * Clobbers x0.
65 * --------------------------------------------------------------------
66 */
67 .macro jump_if_cpu_midr _cpu_midr, _label
68 mrs x0, midr_el1
69 ubfx x0, x0, MIDR_PN_SHIFT, #12
70 cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
71 b.eq \_label
72 .endm
73
74 /* --------------------------------------------------------------------
75 * Platform reset handler for Juno R0.
Sandrine Bailleux798140d2014-07-17 16:06:39 +010076 *
Sandrine Bailleux9d548a22015-11-18 11:10:30 +000077 * Juno R0 has the following topology:
78 * - Quad core Cortex-A53 processor cluster;
79 * - Dual core Cortex-A57 processor cluster.
80 *
81 * This handler does the following:
Sandrine Bailleuxfd8f8982015-02-04 14:06:10 +000082 * - Implement workaround for defect id 831273 by enabling an event
83 * stream every 65536 cycles.
84 * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A57
85 * - Set the L2 Tag RAM latency to 2 (i.e. 3 cycles) for Cortex-A57
Sandrine Bailleuxfd8f8982015-02-04 14:06:10 +000086 * --------------------------------------------------------------------
Sandrine Bailleux798140d2014-07-17 16:06:39 +010087 */
Sandrine Bailleux9d548a22015-11-18 11:10:30 +000088func JUNO_HANDLER(0)
Sandrine Bailleuxfd8f8982015-02-04 14:06:10 +000089 /* --------------------------------------------------------------------
Sandrine Bailleux9d548a22015-11-18 11:10:30 +000090 * Enable the event stream every 65536 cycles
Sandrine Bailleuxfd8f8982015-02-04 14:06:10 +000091 * --------------------------------------------------------------------
92 */
Sandrine Bailleux9d548a22015-11-18 11:10:30 +000093 mov x0, #(0xf << EVNTI_SHIFT)
94 orr x0, x0, #EVNTEN_BIT
95 msr CNTKCTL_EL1, x0
96
97 /* --------------------------------------------------------------------
98 * Nothing else to do on Cortex-A53.
99 * --------------------------------------------------------------------
Sandrine Bailleuxfd8f8982015-02-04 14:06:10 +0000100 */
Sandrine Bailleux9d548a22015-11-18 11:10:30 +0000101 jump_if_cpu_midr CORTEX_A53_MIDR, 1f
Sandrine Bailleuxfd8f8982015-02-04 14:06:10 +0000102
103 /* --------------------------------------------------------------------
Sandrine Bailleux9d548a22015-11-18 11:10:30 +0000104 * Cortex-A57 specific settings
Sandrine Bailleuxfd8f8982015-02-04 14:06:10 +0000105 * --------------------------------------------------------------------
106 */
Sandrine Bailleux9d548a22015-11-18 11:10:30 +0000107 mov x0, #((L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
108 (L2_TAG_RAM_LATENCY_3_CYCLES << L2CTLR_TAG_RAM_LATENCY_SHIFT))
109 msr L2CTLR_EL1, x0
1101:
111 isb
112 ret
113endfunc JUNO_HANDLER(0)
Sandrine Bailleux798140d2014-07-17 16:06:39 +0100114
Sandrine Bailleux9d548a22015-11-18 11:10:30 +0000115 /* --------------------------------------------------------------------
116 * Platform reset handler for Juno R1.
117 *
118 * Juno R1 has the following topology:
119 * - Quad core Cortex-A53 processor cluster;
120 * - Dual core Cortex-A57 processor cluster.
121 *
122 * This handler does the following:
123 * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A57
124 *
125 * Note that:
126 * - The default value for the L2 Tag RAM latency for Cortex-A57 is
127 * suitable.
128 * - Defect #831273 doesn't affect Juno R1.
129 * --------------------------------------------------------------------
130 */
131func JUNO_HANDLER(1)
132 /* --------------------------------------------------------------------
133 * Nothing to do on Cortex-A53.
134 * --------------------------------------------------------------------
135 */
136 jump_if_cpu_midr CORTEX_A57_MIDR, A57
Sandrine Bailleuxfd8f8982015-02-04 14:06:10 +0000137 ret
138
139A57:
140 /* --------------------------------------------------------------------
141 * Cortex-A57 specific settings
142 * --------------------------------------------------------------------
143 */
Sandrine Bailleux9d548a22015-11-18 11:10:30 +0000144 mov x0, #(L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT)
Sandrine Bailleux798140d2014-07-17 16:06:39 +0100145 msr L2CTLR_EL1, x0
Sandrine Bailleux9d548a22015-11-18 11:10:30 +0000146 isb
147 ret
148endfunc JUNO_HANDLER(1)
Sandrine Bailleuxfd8f8982015-02-04 14:06:10 +0000149
Sandrine Bailleuxfd8f8982015-02-04 14:06:10 +0000150 /* --------------------------------------------------------------------
Sandrine Bailleux9d548a22015-11-18 11:10:30 +0000151 * Platform reset handler for Juno R2.
152 *
153 * Juno R2 has the following topology:
154 * - Quad core Cortex-A53 processor cluster;
155 * - Dual core Cortex-A72 processor cluster.
156 *
Sandrine Bailleux29a7a032015-11-18 11:59:35 +0000157 * This handler does the following:
158 * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A72
159 * - Set the L2 Tag RAM latency to 1 (i.e. 2 cycles) for Cortex-A72
160 *
161 * Note that:
162 * - Defect #831273 doesn't affect Juno R2.
Sandrine Bailleuxfd8f8982015-02-04 14:06:10 +0000163 * --------------------------------------------------------------------
Yatharth Kochar36433d12014-11-20 18:09:41 +0000164 */
Sandrine Bailleux9d548a22015-11-18 11:10:30 +0000165func JUNO_HANDLER(2)
Sandrine Bailleux29a7a032015-11-18 11:59:35 +0000166 /* --------------------------------------------------------------------
167 * Nothing to do on Cortex-A53.
168 * --------------------------------------------------------------------
169 */
170 jump_if_cpu_midr CORTEX_A72_MIDR, A72
171 ret
172
173A72:
174 /* --------------------------------------------------------------------
175 * Cortex-A72 specific settings
176 * --------------------------------------------------------------------
177 */
178 mov x0, #((L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
179 (L2_TAG_RAM_LATENCY_2_CYCLES << L2CTLR_TAG_RAM_LATENCY_SHIFT))
180 msr L2CTLR_EL1, x0
181 isb
Sandrine Bailleux798140d2014-07-17 16:06:39 +0100182 ret
Sandrine Bailleux9d548a22015-11-18 11:10:30 +0000183endfunc JUNO_HANDLER(2)
184
185 /* --------------------------------------------------------------------
186 * void plat_reset_handler(void);
187 *
188 * Determine the Juno board revision and call the appropriate reset
189 * handler.
190 * --------------------------------------------------------------------
191 */
192func plat_reset_handler
193 /* Read the V2M SYS_ID register */
194 mov_imm x0, (V2M_SYSREGS_BASE + V2M_SYS_ID)
195 ldr w1, [x0]
196 /* Extract board revision from the SYS_ID */
197 ubfx x0, x1, #V2M_SYS_ID_REV_SHIFT, #4
198
199 JUMP_TO_HANDLER_IF_JUNO_R(0)
200 JUMP_TO_HANDLER_IF_JUNO_R(1)
201 JUMP_TO_HANDLER_IF_JUNO_R(2)
202
203 /* Board revision is not supported */
204not_supported:
205 b not_supported
206
Kévin Petita877c252015-03-24 14:03:57 +0000207endfunc plat_reset_handler
David Wang323ebe82015-10-22 13:30:50 +0800208
209 /* -----------------------------------------------------
210 * unsigned int plat_arm_calc_core_pos(uint64_t mpidr)
211 * Helper function to calculate the core position.
212 * -----------------------------------------------------
213 */
214func plat_arm_calc_core_pos
215 b css_calc_core_pos_swap_cluster
216endfunc plat_arm_calc_core_pos