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Varun Wadekar28dcc212016-07-20 10:28:51 -07001/*
Manish V Badarkhe1af10a22020-07-24 02:05:24 +01002 * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
Varun Wadekar3923f882020-05-12 14:04:10 -07003 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
Varun Wadekar28dcc212016-07-20 10:28:51 -07004 *
dp-armfa3cf0b2017-05-03 09:38:09 +01005 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekar28dcc212016-07-20 10:28:51 -07006 */
7
8#include <arch_helpers.h>
Anthony Zhou70262ef2017-03-22 14:37:04 +08009#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <lib/mmio.h>
Manish V Badarkhe1af10a22020-07-24 02:05:24 +010011#include <lib/smccc.h>
12#include <services/arm_arch_svc.h>
Varun Wadekar28dcc212016-07-20 10:28:51 -070013#include <tegra_def.h>
14#include <tegra_platform.h>
15#include <tegra_private.h>
16
17/*******************************************************************************
18 * Tegra platforms
19 ******************************************************************************/
20typedef enum tegra_platform {
Anthony Zhou4408e882017-07-07 14:29:51 +080021 TEGRA_PLATFORM_SILICON = 0U,
Varun Wadekar28dcc212016-07-20 10:28:51 -070022 TEGRA_PLATFORM_QT,
23 TEGRA_PLATFORM_FPGA,
24 TEGRA_PLATFORM_EMULATION,
Anthony Zhou70262ef2017-03-22 14:37:04 +080025 TEGRA_PLATFORM_LINSIM,
26 TEGRA_PLATFORM_UNIT_FPGA,
27 TEGRA_PLATFORM_VIRT_DEV_KIT,
Varun Wadekar28dcc212016-07-20 10:28:51 -070028 TEGRA_PLATFORM_MAX,
29} tegra_platform_t;
30
31/*******************************************************************************
32 * Tegra macros defining all the SoC minor versions
33 ******************************************************************************/
Anthony Zhou70262ef2017-03-22 14:37:04 +080034#define TEGRA_MINOR_QT U(0)
35#define TEGRA_MINOR_FPGA U(1)
36#define TEGRA_MINOR_ASIM_QT U(2)
37#define TEGRA_MINOR_ASIM_LINSIM U(3)
38#define TEGRA_MINOR_DSIM_ASIM_LINSIM U(4)
39#define TEGRA_MINOR_UNIT_FPGA U(5)
40#define TEGRA_MINOR_VIRT_DEV_KIT U(6)
Varun Wadekar28dcc212016-07-20 10:28:51 -070041
42/*******************************************************************************
Anthony Zhou70262ef2017-03-22 14:37:04 +080043 * Tegra macros defining all the SoC pre_si_platform
44 ******************************************************************************/
45#define TEGRA_PRE_SI_QT U(1)
46#define TEGRA_PRE_SI_FPGA U(2)
47#define TEGRA_PRE_SI_UNIT_FPGA U(3)
48#define TEGRA_PRE_SI_ASIM_QT U(4)
49#define TEGRA_PRE_SI_ASIM_LINSIM U(5)
50#define TEGRA_PRE_SI_DSIM_ASIM_LINSIM U(6)
51#define TEGRA_PRE_SI_VDK U(8)
Varun Wadekar28dcc212016-07-20 10:28:51 -070052
Varun Wadekar28dcc212016-07-20 10:28:51 -070053/*
54 * Read the chip ID value
55 */
56static uint32_t tegra_get_chipid(void)
57{
58 return mmio_read_32(TEGRA_MISC_BASE + HARDWARE_REVISION_OFFSET);
59}
60
61/*
62 * Read the chip's major version from chip ID value
63 */
Varun Wadekarfc9b91e2017-03-10 09:53:37 -080064uint32_t tegra_get_chipid_major(void)
Varun Wadekar28dcc212016-07-20 10:28:51 -070065{
66 return (tegra_get_chipid() >> MAJOR_VERSION_SHIFT) & MAJOR_VERSION_MASK;
67}
68
69/*
70 * Read the chip's minor version from the chip ID value
71 */
Varun Wadekarfc9b91e2017-03-10 09:53:37 -080072uint32_t tegra_get_chipid_minor(void)
Varun Wadekar28dcc212016-07-20 10:28:51 -070073{
74 return (tegra_get_chipid() >> MINOR_VERSION_SHIFT) & MINOR_VERSION_MASK;
75}
76
Marvin Hsu589a7e12017-04-12 20:40:27 +080077/*
78 * Read the chip's pre_si_platform valus from the chip ID value
79 */
80static uint32_t tegra_get_chipid_pre_si_platform(void)
Varun Wadekar28dcc212016-07-20 10:28:51 -070081{
Marvin Hsu589a7e12017-04-12 20:40:27 +080082 return (tegra_get_chipid() >> PRE_SI_PLATFORM_SHIFT) & PRE_SI_PLATFORM_MASK;
83}
Varun Wadekar28dcc212016-07-20 10:28:51 -070084
Marvin Hsu589a7e12017-04-12 20:40:27 +080085bool tegra_chipid_is_t132(void)
86{
87 uint32_t chip_id = ((tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK);
88
Anthony Zhou4408e882017-07-07 14:29:51 +080089 return (chip_id == TEGRA_CHIPID_TEGRA13);
Varun Wadekar28dcc212016-07-20 10:28:51 -070090}
91
Marvin Hsu589a7e12017-04-12 20:40:27 +080092bool tegra_chipid_is_t186(void)
Varun Wadekar28dcc212016-07-20 10:28:51 -070093{
94 uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK;
95
Marvin Hsu589a7e12017-04-12 20:40:27 +080096 return (chip_id == TEGRA_CHIPID_TEGRA18);
Varun Wadekar28dcc212016-07-20 10:28:51 -070097}
98
Marvin Hsu589a7e12017-04-12 20:40:27 +080099bool tegra_chipid_is_t210(void)
Varun Wadekarfdcdfe22017-04-13 14:12:49 -0700100{
101 uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK;
102
Anthony Zhou4408e882017-07-07 14:29:51 +0800103 return (chip_id == TEGRA_CHIPID_TEGRA21);
Varun Wadekarfdcdfe22017-04-13 14:12:49 -0700104}
105
Marvin Hsu589a7e12017-04-12 20:40:27 +0800106bool tegra_chipid_is_t210_b01(void)
Anthony Zhou70262ef2017-03-22 14:37:04 +0800107{
Anthony Zhou4408e882017-07-07 14:29:51 +0800108 return (tegra_chipid_is_t210() && (tegra_get_chipid_major() == 0x2U));
Anthony Zhou70262ef2017-03-22 14:37:04 +0800109}
110
111/*
Varun Wadekar28dcc212016-07-20 10:28:51 -0700112 * Read the chip ID value and derive the platform
113 */
114static tegra_platform_t tegra_get_platform(void)
115{
Anthony Zhou70262ef2017-03-22 14:37:04 +0800116 uint32_t major, minor, pre_si_platform;
117 tegra_platform_t ret;
118
119 /* get the major/minor chip ID values */
120 major = tegra_get_chipid_major();
121 minor = tegra_get_chipid_minor();
122 pre_si_platform = tegra_get_chipid_pre_si_platform();
123
124 if (major == 0U) {
125 /*
126 * The minor version number is used by simulation platforms
127 */
128 switch (minor) {
129 /*
130 * Cadence's QuickTurn emulation system is a Solaris-based
131 * chip emulation system
132 */
133 case TEGRA_MINOR_QT:
134 case TEGRA_MINOR_ASIM_QT:
135 ret = TEGRA_PLATFORM_QT;
136 break;
137
138 /*
139 * FPGAs are used during early software/hardware development
140 */
141 case TEGRA_MINOR_FPGA:
142 ret = TEGRA_PLATFORM_FPGA;
143 break;
144 /*
145 * Linsim is a reconfigurable, clock-driven, mixed RTL/cmodel
146 * simulation framework.
147 */
148 case TEGRA_MINOR_ASIM_LINSIM:
149 case TEGRA_MINOR_DSIM_ASIM_LINSIM:
150 ret = TEGRA_PLATFORM_LINSIM;
151 break;
Varun Wadekar28dcc212016-07-20 10:28:51 -0700152
Anthony Zhou70262ef2017-03-22 14:37:04 +0800153 /*
154 * Unit FPGAs run the actual hardware block IP on the FPGA with
155 * the other parts of the system using Linsim.
156 */
157 case TEGRA_MINOR_UNIT_FPGA:
158 ret = TEGRA_PLATFORM_UNIT_FPGA;
159 break;
160 /*
161 * The Virtualizer Development Kit (VDK) is the standard chip
162 * development from Synopsis.
163 */
164 case TEGRA_MINOR_VIRT_DEV_KIT:
165 ret = TEGRA_PLATFORM_VIRT_DEV_KIT;
166 break;
Marvin Hsu589a7e12017-04-12 20:40:27 +0800167
Anthony Zhou70262ef2017-03-22 14:37:04 +0800168 default:
Anthony Zhou70262ef2017-03-22 14:37:04 +0800169 ret = TEGRA_PLATFORM_MAX;
170 break;
171 }
Varun Wadekar28dcc212016-07-20 10:28:51 -0700172
Anthony Zhou70262ef2017-03-22 14:37:04 +0800173 } else if (pre_si_platform > 0U) {
Varun Wadekar28dcc212016-07-20 10:28:51 -0700174
Anthony Zhou70262ef2017-03-22 14:37:04 +0800175 switch (pre_si_platform) {
176 /*
177 * Cadence's QuickTurn emulation system is a Solaris-based
178 * chip emulation system
179 */
180 case TEGRA_PRE_SI_QT:
181 case TEGRA_PRE_SI_ASIM_QT:
182 ret = TEGRA_PLATFORM_QT;
183 break;
Varun Wadekar28dcc212016-07-20 10:28:51 -0700184
Anthony Zhou70262ef2017-03-22 14:37:04 +0800185 /*
186 * FPGAs are used during early software/hardware development
187 */
188 case TEGRA_PRE_SI_FPGA:
189 ret = TEGRA_PLATFORM_FPGA;
190 break;
191 /*
192 * Linsim is a reconfigurable, clock-driven, mixed RTL/cmodel
193 * simulation framework.
194 */
195 case TEGRA_PRE_SI_ASIM_LINSIM:
196 case TEGRA_PRE_SI_DSIM_ASIM_LINSIM:
197 ret = TEGRA_PLATFORM_LINSIM;
198 break;
Varun Wadekar28dcc212016-07-20 10:28:51 -0700199
Anthony Zhou70262ef2017-03-22 14:37:04 +0800200 /*
201 * Unit FPGAs run the actual hardware block IP on the FPGA with
202 * the other parts of the system using Linsim.
203 */
204 case TEGRA_PRE_SI_UNIT_FPGA:
205 ret = TEGRA_PLATFORM_UNIT_FPGA;
206 break;
207 /*
208 * The Virtualizer Development Kit (VDK) is the standard chip
209 * development from Synopsis.
210 */
211 case TEGRA_PRE_SI_VDK:
212 ret = TEGRA_PLATFORM_VIRT_DEV_KIT;
213 break;
Varun Wadekar28dcc212016-07-20 10:28:51 -0700214
Anthony Zhou70262ef2017-03-22 14:37:04 +0800215 default:
Anthony Zhou70262ef2017-03-22 14:37:04 +0800216 ret = TEGRA_PLATFORM_MAX;
217 break;
218 }
219
220 } else {
221 /* Actual silicon platforms have a non-zero major version */
222 ret = TEGRA_PLATFORM_SILICON;
223 }
224
225 return ret;
226}
227
228bool tegra_platform_is_silicon(void)
229{
230 return ((tegra_get_platform() == TEGRA_PLATFORM_SILICON) ? true : false);
Varun Wadekar28dcc212016-07-20 10:28:51 -0700231}
232
Anthony Zhou70262ef2017-03-22 14:37:04 +0800233bool tegra_platform_is_qt(void)
Varun Wadekar28dcc212016-07-20 10:28:51 -0700234{
Anthony Zhou70262ef2017-03-22 14:37:04 +0800235 return ((tegra_get_platform() == TEGRA_PLATFORM_QT) ? true : false);
Varun Wadekar28dcc212016-07-20 10:28:51 -0700236}
237
Anthony Zhou70262ef2017-03-22 14:37:04 +0800238bool tegra_platform_is_linsim(void)
Varun Wadekar28dcc212016-07-20 10:28:51 -0700239{
Anthony Zhou70262ef2017-03-22 14:37:04 +0800240 tegra_platform_t plat = tegra_get_platform();
241
242 return (((plat == TEGRA_PLATFORM_LINSIM) ||
243 (plat == TEGRA_PLATFORM_UNIT_FPGA)) ? true : false);
Varun Wadekar28dcc212016-07-20 10:28:51 -0700244}
245
Anthony Zhou70262ef2017-03-22 14:37:04 +0800246bool tegra_platform_is_fpga(void)
Varun Wadekar28dcc212016-07-20 10:28:51 -0700247{
Anthony Zhou70262ef2017-03-22 14:37:04 +0800248 return ((tegra_get_platform() == TEGRA_PLATFORM_FPGA) ? true : false);
Varun Wadekar28dcc212016-07-20 10:28:51 -0700249}
250
Anthony Zhou70262ef2017-03-22 14:37:04 +0800251bool tegra_platform_is_emulation(void)
Varun Wadekar28dcc212016-07-20 10:28:51 -0700252{
253 return (tegra_get_platform() == TEGRA_PLATFORM_EMULATION);
254}
Anthony Zhou70262ef2017-03-22 14:37:04 +0800255
256bool tegra_platform_is_unit_fpga(void)
257{
258 return ((tegra_get_platform() == TEGRA_PLATFORM_UNIT_FPGA) ? true : false);
259}
260
261bool tegra_platform_is_virt_dev_kit(void)
262{
263 return ((tegra_get_platform() == TEGRA_PLATFORM_VIRT_DEV_KIT) ? true : false);
264}
Varun Wadekar3923f882020-05-12 14:04:10 -0700265
266/*
267 * This function returns soc version which mainly consist of below fields
268 *
269 * soc_version[30:24] = JEP-106 continuation code for the SiP
270 * soc_version[23:16] = JEP-106 identification code with parity bit for the SiP
271 * soc_version[0:15] = chip identification
272 */
273int32_t plat_get_soc_version(void)
274{
275 uint32_t chip_id = ((tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK);
276 uint32_t manfid = (JEDEC_NVIDIA_BKID << 24) | (JEDEC_NVIDIA_MFID << 16);
277
278 return (int32_t)(manfid | (chip_id & 0xFFFF));
279}
280
281/*
282 * This function returns soc revision in below format
283 *
284 * soc_revision[8:15] = major version number
285 * soc_revision[0:7] = minor version number
286 */
287int32_t plat_get_soc_revision(void)
288{
289 return (int32_t)((tegra_get_chipid_major() << 8) | tegra_get_chipid_minor());
290}
Manish V Badarkhe1af10a22020-07-24 02:05:24 +0100291
292/*****************************************************************************
293 * plat_smccc_feature_available() - This function checks whether SMCCC feature
294 * is availabile for the platform or not.
295 * @fid: SMCCC function id
296 *
297 * Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and
298 * SMC_ARCH_CALL_NOT_SUPPORTED otherwise.
299 *****************************************************************************/
300int32_t plat_smccc_feature_available(u_register_t fid)
301{
302 switch (fid) {
303 case SMCCC_ARCH_SOC_ID:
304 return SMC_ARCH_CALL_SUCCESS;
305 default:
306 return SMC_ARCH_CALL_NOT_SUPPORTED;
307 }
308}