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git01.mediatek.com / filogic / atf / c61094ba8959ad20ed1947ca94cb4ad5d3059637 / . / plat / nvidia / tegra / soc / t186 / plat_smmu.c
blob: b4a7fe5969bef4869a659ebbaf3826c20a89da73 [file] [log] [blame]
Pritesh Raithathac88654f2017-01-02 20:11:32 +0530[diff] [blame]1/*
Antonio Nino Diaz14ba9632018-03-08 10:57:43 +0000[diff] [blame]2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
Pritesh Raithathac88654f2017-01-02 20:11:32 +0530[diff] [blame]3 *
Antonio Nino Diaz14ba9632018-03-08 10:57:43 +0000[diff] [blame]4 * SPDX-License-Identifier: BSD-3-Clause
Pritesh Raithathac88654f2017-01-02 20:11:32 +0530[diff] [blame]5 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]7#include <common/bl_common.h>
8
Pritesh Raithathac88654f2017-01-02 20:11:32 +0530[diff] [blame]9#include <smmu.h>
10#include <tegra_def.h>
Puneet Saxenacf8c0e22017-08-04 17:19:55 +0530[diff] [blame]11#include <tegra_mc_def.h>
Pritesh Raithathac88654f2017-01-02 20:11:32 +0530[diff] [blame]12
Steven Kao7fd30f52017-07-25 11:29:46 +0800[diff] [blame]13#define MAX_NUM_SMMU_DEVICES U(1)
14
Pritesh Raithathac88654f2017-01-02 20:11:32 +0530[diff] [blame]15/*******************************************************************************
16 * Array to hold SMMU context for Tegra186
17 ******************************************************************************/
18static __attribute__((aligned(16))) smmu_regs_t tegra186_smmu_context[] = {
19 _START_OF_TABLE_,
20 mc_make_sid_security_cfg(SCEW),
21 mc_make_sid_security_cfg(AFIR),
22 mc_make_sid_security_cfg(NVDISPLAYR1),
23 mc_make_sid_security_cfg(XUSB_DEVR),
24 mc_make_sid_security_cfg(VICSRD1),
25 mc_make_sid_security_cfg(NVENCSWR),
26 mc_make_sid_security_cfg(TSECSRDB),
27 mc_make_sid_security_cfg(AXISW),
28 mc_make_sid_security_cfg(SDMMCWAB),
29 mc_make_sid_security_cfg(AONDMAW),
30 mc_make_sid_security_cfg(GPUSWR2),
31 mc_make_sid_security_cfg(SATAW),
32 mc_make_sid_security_cfg(UFSHCW),
33 mc_make_sid_security_cfg(AFIW),
34 mc_make_sid_security_cfg(SDMMCR),
35 mc_make_sid_security_cfg(SCEDMAW),
36 mc_make_sid_security_cfg(UFSHCR),
37 mc_make_sid_security_cfg(SDMMCWAA),
38 mc_make_sid_security_cfg(APEDMAW),
39 mc_make_sid_security_cfg(SESWR),
40 mc_make_sid_security_cfg(MPCORER),
41 mc_make_sid_security_cfg(PTCR),
42 mc_make_sid_security_cfg(BPMPW),
43 mc_make_sid_security_cfg(ETRW),
44 mc_make_sid_security_cfg(GPUSRD),
45 mc_make_sid_security_cfg(VICSWR),
46 mc_make_sid_security_cfg(SCEDMAR),
47 mc_make_sid_security_cfg(HDAW),
48 mc_make_sid_security_cfg(ISPWA),
49 mc_make_sid_security_cfg(EQOSW),
50 mc_make_sid_security_cfg(XUSB_HOSTW),
51 mc_make_sid_security_cfg(TSECSWR),
52 mc_make_sid_security_cfg(SDMMCRAA),
53 mc_make_sid_security_cfg(APER),
54 mc_make_sid_security_cfg(VIW),
55 mc_make_sid_security_cfg(APEW),
56 mc_make_sid_security_cfg(AXISR),
57 mc_make_sid_security_cfg(SDMMCW),
58 mc_make_sid_security_cfg(BPMPDMAW),
59 mc_make_sid_security_cfg(ISPRA),
60 mc_make_sid_security_cfg(NVDECSWR),
61 mc_make_sid_security_cfg(XUSB_DEVW),
62 mc_make_sid_security_cfg(NVDECSRD),
63 mc_make_sid_security_cfg(MPCOREW),
64 mc_make_sid_security_cfg(NVDISPLAYR),
65 mc_make_sid_security_cfg(BPMPDMAR),
66 mc_make_sid_security_cfg(NVJPGSWR),
67 mc_make_sid_security_cfg(NVDECSRD1),
68 mc_make_sid_security_cfg(TSECSRD),
69 mc_make_sid_security_cfg(NVJPGSRD),
70 mc_make_sid_security_cfg(SDMMCWA),
71 mc_make_sid_security_cfg(SCER),
72 mc_make_sid_security_cfg(XUSB_HOSTR),
73 mc_make_sid_security_cfg(VICSRD),
74 mc_make_sid_security_cfg(AONDMAR),
75 mc_make_sid_security_cfg(AONW),
76 mc_make_sid_security_cfg(SDMMCRA),
77 mc_make_sid_security_cfg(HOST1XDMAR),
78 mc_make_sid_security_cfg(EQOSR),
79 mc_make_sid_security_cfg(SATAR),
80 mc_make_sid_security_cfg(BPMPR),
81 mc_make_sid_security_cfg(HDAR),
82 mc_make_sid_security_cfg(SDMMCRAB),
83 mc_make_sid_security_cfg(ETRR),
84 mc_make_sid_security_cfg(AONR),
85 mc_make_sid_security_cfg(APEDMAR),
86 mc_make_sid_security_cfg(SESRD),
87 mc_make_sid_security_cfg(NVENCSRD),
88 mc_make_sid_security_cfg(GPUSWR),
89 mc_make_sid_security_cfg(TSECSWRB),
90 mc_make_sid_security_cfg(ISPWB),
91 mc_make_sid_security_cfg(GPUSRD2),
92 mc_make_sid_override_cfg(APER),
93 mc_make_sid_override_cfg(VICSRD),
94 mc_make_sid_override_cfg(NVENCSRD),
95 mc_make_sid_override_cfg(NVJPGSWR),
96 mc_make_sid_override_cfg(AONW),
97 mc_make_sid_override_cfg(BPMPR),
98 mc_make_sid_override_cfg(BPMPW),
99 mc_make_sid_override_cfg(HDAW),
100 mc_make_sid_override_cfg(NVDISPLAYR1),
101 mc_make_sid_override_cfg(APEDMAR),
102 mc_make_sid_override_cfg(AFIR),
103 mc_make_sid_override_cfg(AXISR),
104 mc_make_sid_override_cfg(VICSRD1),
105 mc_make_sid_override_cfg(TSECSRD),
106 mc_make_sid_override_cfg(BPMPDMAW),
107 mc_make_sid_override_cfg(MPCOREW),
108 mc_make_sid_override_cfg(XUSB_HOSTR),
109 mc_make_sid_override_cfg(GPUSWR),
110 mc_make_sid_override_cfg(XUSB_DEVR),
111 mc_make_sid_override_cfg(UFSHCW),
112 mc_make_sid_override_cfg(XUSB_HOSTW),
113 mc_make_sid_override_cfg(SDMMCWAB),
114 mc_make_sid_override_cfg(SATAW),
115 mc_make_sid_override_cfg(SCEDMAR),
116 mc_make_sid_override_cfg(HOST1XDMAR),
117 mc_make_sid_override_cfg(SDMMCWA),
118 mc_make_sid_override_cfg(APEDMAW),
119 mc_make_sid_override_cfg(SESWR),
120 mc_make_sid_override_cfg(AXISW),
121 mc_make_sid_override_cfg(AONDMAW),
122 mc_make_sid_override_cfg(TSECSWRB),
123 mc_make_sid_override_cfg(MPCORER),
124 mc_make_sid_override_cfg(ISPWB),
125 mc_make_sid_override_cfg(AONR),
126 mc_make_sid_override_cfg(BPMPDMAR),
127 mc_make_sid_override_cfg(HDAR),
128 mc_make_sid_override_cfg(SDMMCRA),
129 mc_make_sid_override_cfg(ETRW),
130 mc_make_sid_override_cfg(GPUSWR2),
131 mc_make_sid_override_cfg(EQOSR),
132 mc_make_sid_override_cfg(TSECSWR),
133 mc_make_sid_override_cfg(ETRR),
134 mc_make_sid_override_cfg(NVDECSRD),
135 mc_make_sid_override_cfg(TSECSRDB),
136 mc_make_sid_override_cfg(SDMMCRAA),
137 mc_make_sid_override_cfg(NVDECSRD1),
138 mc_make_sid_override_cfg(SDMMCR),
139 mc_make_sid_override_cfg(NVJPGSRD),
140 mc_make_sid_override_cfg(SCEDMAW),
141 mc_make_sid_override_cfg(SDMMCWAA),
142 mc_make_sid_override_cfg(APEW),
143 mc_make_sid_override_cfg(AONDMAR),
144 mc_make_sid_override_cfg(PTCR),
145 mc_make_sid_override_cfg(SCER),
146 mc_make_sid_override_cfg(ISPRA),
147 mc_make_sid_override_cfg(ISPWA),
148 mc_make_sid_override_cfg(VICSWR),
149 mc_make_sid_override_cfg(SESRD),
150 mc_make_sid_override_cfg(SDMMCW),
151 mc_make_sid_override_cfg(SDMMCRAB),
152 mc_make_sid_override_cfg(EQOSW),
153 mc_make_sid_override_cfg(GPUSRD2),
154 mc_make_sid_override_cfg(SCEW),
155 mc_make_sid_override_cfg(GPUSRD),
156 mc_make_sid_override_cfg(NVDECSWR),
157 mc_make_sid_override_cfg(XUSB_DEVW),
158 mc_make_sid_override_cfg(SATAR),
159 mc_make_sid_override_cfg(NVDISPLAYR),
160 mc_make_sid_override_cfg(VIW),
161 mc_make_sid_override_cfg(UFSHCR),
162 mc_make_sid_override_cfg(NVENCSWR),
163 mc_make_sid_override_cfg(AFIW),
Pritesh Raithatha24370712017-10-26 16:59:58 +0530[diff] [blame]164 smmu_make_cfg(TEGRA_SMMU0_BASE),
Pritesh Raithathac88654f2017-01-02 20:11:32 +0530[diff] [blame]165 smmu_bypass_cfg, /* TBU settings */
166 _END_OF_TABLE_,
167};
168
169/*******************************************************************************
170 * Handler to return the pointer to the SMMU's context struct
171 ******************************************************************************/
172smmu_regs_t *plat_get_smmu_ctx(void)
173{
174 /* index of _END_OF_TABLE_ */
Anthony Zhou5a4ce002017-06-28 16:49:16 +0800[diff] [blame]175 tegra186_smmu_context[0].val = (uint32_t)(ARRAY_SIZE(tegra186_smmu_context)) - 1U;
Pritesh Raithathac88654f2017-01-02 20:11:32 +0530[diff] [blame]176
177 return tegra186_smmu_context;
178}
Steven Kao7fd30f52017-07-25 11:29:46 +0800[diff] [blame]179
180/*******************************************************************************
181 * Handler to return the support SMMU devices number
182 ******************************************************************************/
183uint32_t plat_get_num_smmu_devices(void)
184{
185 return MAX_NUM_SMMU_DEVICES;
186}