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Andre Przywara6d471e12019-07-09 11:25:57 +01001/*
2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <assert_macros.S>
10#include <platform_def.h>
11#include <cortex_a72.h>
12
13#include "../include/rpi_hw.h"
14
15 .globl plat_crash_console_flush
16 .globl plat_crash_console_init
17 .globl plat_crash_console_putc
18 .globl platform_mem_init
19 .globl plat_get_my_entrypoint
20 .globl plat_is_my_cpu_primary
21 .globl plat_my_core_pos
22 .globl plat_reset_handler
23 .globl plat_rpi3_calc_core_pos
24 .globl plat_secondary_cold_boot_setup
25
26 /* -----------------------------------------------------
27 * unsigned int plat_my_core_pos(void)
28 *
29 * This function uses the plat_rpi3_calc_core_pos()
30 * definition to get the index of the calling CPU.
31 * -----------------------------------------------------
32 */
33func plat_my_core_pos
34 mrs x0, mpidr_el1
35 b plat_rpi3_calc_core_pos
36endfunc plat_my_core_pos
37
38 /* -----------------------------------------------------
39 * unsigned int plat_rpi3_calc_core_pos(u_register_t mpidr);
40 *
41 * CorePos = (ClusterId * 4) + CoreId
42 * -----------------------------------------------------
43 */
44func plat_rpi3_calc_core_pos
45 and x1, x0, #MPIDR_CPU_MASK
46 and x0, x0, #MPIDR_CLUSTER_MASK
47 add x0, x1, x0, LSR #6
48 ret
49endfunc plat_rpi3_calc_core_pos
50
51 /* -----------------------------------------------------
52 * unsigned int plat_is_my_cpu_primary (void);
53 *
54 * Find out whether the current cpu is the primary
55 * cpu.
56 * -----------------------------------------------------
57 */
58func plat_is_my_cpu_primary
59 mrs x0, mpidr_el1
60 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
61 cmp x0, #RPI4_PRIMARY_CPU
62 cset w0, eq
63 ret
64endfunc plat_is_my_cpu_primary
65
66 /* -----------------------------------------------------
67 * void plat_secondary_cold_boot_setup (void);
68 *
69 * This function performs any platform specific actions
70 * needed for a secondary cpu after a cold reset e.g
71 * mark the cpu's presence, mechanism to place it in a
72 * holding pen etc.
73 * -----------------------------------------------------
74 */
75func plat_secondary_cold_boot_setup
76 /* Calculate address of our hold entry */
77 bl plat_my_core_pos
78 lsl x0, x0, #3
79 mov_imm x2, PLAT_RPI3_TM_HOLD_BASE
80 add x0, x0, x2
81
82 /*
83 * This code runs way before requesting the warmboot of this core,
84 * so it is possible to clear the mailbox before getting a request
85 * to boot.
86 */
87 mov x1, PLAT_RPI3_TM_HOLD_STATE_WAIT
88 str x1,[x0]
89
90 /* Wait until we have a go */
91poll_mailbox:
92 wfe
93 ldr x1, [x0]
94 cmp x1, PLAT_RPI3_TM_HOLD_STATE_GO
95 bne poll_mailbox
96
97 /* Jump to the provided entrypoint */
98 mov_imm x0, PLAT_RPI3_TM_ENTRYPOINT
99 ldr x1, [x0]
100 br x1
101endfunc plat_secondary_cold_boot_setup
102
103 /* ---------------------------------------------------------------------
104 * uintptr_t plat_get_my_entrypoint (void);
105 *
106 * Main job of this routine is to distinguish between a cold and a warm
107 * boot.
108 *
109 * This functions returns:
110 * - 0 for a cold boot.
111 * - Any other value for a warm boot.
112 * ---------------------------------------------------------------------
113 */
114func plat_get_my_entrypoint
115 /* TODO: support warm boot */
116 mov x0, #0
117 ret
118endfunc plat_get_my_entrypoint
119
120 /* ---------------------------------------------
121 * void platform_mem_init (void);
122 *
123 * No need to carry out any memory initialization.
124 * ---------------------------------------------
125 */
126func platform_mem_init
127 ret
128endfunc platform_mem_init
129
130 /* ---------------------------------------------
131 * int plat_crash_console_init(void)
132 * Function to initialize the crash console
133 * without a C Runtime to print crash report.
134 * Clobber list : x0 - x3
135 * ---------------------------------------------
136 */
137func plat_crash_console_init
138 mov_imm x0, PLAT_RPI3_UART_BASE
Andre Przywaraeb10a862019-12-12 16:31:11 +0000139 mov x1, xzr
140 mov x2, xzr
Andre Przywara6d471e12019-07-09 11:25:57 +0100141 b console_16550_core_init
142endfunc plat_crash_console_init
143
144 /* ---------------------------------------------
145 * int plat_crash_console_putc(int c)
146 * Function to print a character on the crash
147 * console without a C Runtime.
148 * Clobber list : x1, x2
149 * ---------------------------------------------
150 */
151func plat_crash_console_putc
152 mov_imm x1, PLAT_RPI3_UART_BASE
153 b console_16550_core_putc
154endfunc plat_crash_console_putc
155
156 /* ---------------------------------------------
157 * int plat_crash_console_flush()
158 * Function to force a write of all buffered
159 * data that hasn't been output.
160 * Out : return -1 on error else return 0.
161 * Clobber list : x0, x1
162 * ---------------------------------------------
163 */
164func plat_crash_console_flush
165 mov_imm x0, PLAT_RPI3_UART_BASE
166 b console_16550_core_flush
167endfunc plat_crash_console_flush
168
169 /* ---------------------------------------------
170 * void plat_reset_handler(void);
171 * ---------------------------------------------
172 */
173func plat_reset_handler
174 /* ------------------------------------------------
175 * Set L2 read/write cache latency:
176 * - L2 Data RAM latency: 3 cycles (0b010)
177 * - L2 Data RAM setup: 1 cycle (bit 5)
178 * ------------------------------------------------
179 */
180 mrs x0, CORTEX_A72_L2CTLR_EL1
181 mov x1, #0x22
182 orr x0, x0, x1
183 msr CORTEX_A72_L2CTLR_EL1, x0
184 isb
185
186 ret
187endfunc plat_reset_handler