Dimitris Papastamos | e08005a | 2017-10-12 13:02:29 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <amu.h> |
| 8 | #include <arch.h> |
| 9 | #include <arch_helpers.h> |
| 10 | |
| 11 | void amu_enable(int el2_unused) |
| 12 | { |
| 13 | uint64_t features; |
| 14 | |
| 15 | features = read_id_aa64pfr0_el1() >> ID_AA64PFR0_AMU_SHIFT; |
| 16 | if ((features & ID_AA64PFR0_AMU_MASK) == 1) { |
| 17 | uint64_t v; |
| 18 | |
| 19 | if (el2_unused) { |
| 20 | /* |
| 21 | * CPTR_EL2.TAM: Set to zero so any accesses to |
| 22 | * the Activity Monitor registers do not trap to EL2. |
| 23 | */ |
| 24 | v = read_cptr_el2(); |
| 25 | v &= ~CPTR_EL2_TAM_BIT; |
| 26 | write_cptr_el2(v); |
| 27 | } |
| 28 | |
| 29 | /* |
| 30 | * CPTR_EL3.TAM: Set to zero so that any accesses to |
| 31 | * the Activity Monitor registers do not trap to EL3. |
| 32 | */ |
| 33 | v = read_cptr_el3(); |
| 34 | v &= ~TAM_BIT; |
| 35 | write_cptr_el3(v); |
| 36 | |
| 37 | /* Enable group 0 counters */ |
| 38 | write_amcntenset0_el0(AMU_GROUP0_COUNTERS_MASK); |
| 39 | } |
| 40 | } |