blob: 021165a4a3cb5954063c296d61a803eaac2b58e3 [file] [log] [blame]
XiaoDong Huang83f79a82019-06-13 10:55:50 +08001/*
2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef __PX30_DEF_H__
8#define __PX30_DEF_H__
9
10#define MAJOR_VERSION (1)
11#define MINOR_VERSION (0)
12
13#define SIZE_K(n) ((n) * 1024)
14
15#define WITH_16BITS_WMSK(bits) (0xffff0000 | (bits))
16
17/* Special value used to verify platform parameters from BL2 to BL3-1 */
18#define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
19
20#define PMU_BASE 0xff000000
21#define PMU_SIZE SIZE_K(64)
22
23#define PMUGRF_BASE 0xff010000
24#define PMUGRF_SIZE SIZE_K(64)
25
26#define PMUSRAM_BASE 0xff020000
27#define PMUSRAM_SIZE SIZE_K(64)
28#define PMUSRAM_RSIZE SIZE_K(8)
29
30#define UART0_BASE 0xff030000
31#define UART0_SIZE SIZE_K(64)
32
33#define GPIO0_BASE 0xff040000
34#define GPIO0_SIZE SIZE_K(64)
35
36#define PMUSGRF_BASE 0xff050000
37#define PMUSGRF_SIZE SIZE_K(64)
38
39#define INTSRAM_BASE 0xff0e0000
40#define INTSRAM_SIZE SIZE_K(64)
41
42#define SGRF_BASE 0xff11c000
43#define SGRF_SIZE SIZE_K(16)
44
45#define GIC400_BASE 0xff130000
46#define GIC400_SIZE SIZE_K(64)
47
48#define GRF_BASE 0xff140000
49#define GRF_SIZE SIZE_K(64)
50
51#define UART1_BASE 0xff158000
52#define UART1_SIZE SIZE_K(64)
53
54#define UART2_BASE 0xff160000
55#define UART2_SIZE SIZE_K(64)
56
57#define I2C0_BASE 0xff180000
58#define I2C0_SIZE SIZE_K(64)
59
60#define PWM0_BASE 0xff200000
61#define PWM0_SIZE SIZE_K(32)
62
63#define PWM1_BASE 0xff208000
64#define PWM1_SIZE SIZE_K(32)
65
66#define NTIME_BASE 0xff210000
67#define NTIME_SIZE SIZE_K(64)
68
69#define STIME_BASE 0xff220000
70#define STIME_SIZE SIZE_K(64)
71
72#define DCF_BASE 0xff230000
73#define DCF_SIZE SIZE_K(64)
74
75#define GPIO1_BASE 0xff250000
76#define GPIO1_SIZE SIZE_K(64)
77
78#define GPIO2_BASE 0xff260000
79#define GPIO2_SIZE SIZE_K(64)
80
81#define GPIO3_BASE 0xff270000
82#define GPIO3_SIZE SIZE_K(64)
83
84#define DDR_PHY_BASE 0xff2a0000
85#define DDR_PHY_SIZE SIZE_K(64)
86
87#define CRU_BASE 0xff2b0000
88#define CRU_SIZE SIZE_K(32)
89
90#define CRU_BOOST_BASE 0xff2b8000
91#define CRU_BOOST_SIZE SIZE_K(16)
92
93#define PMUCRU_BASE 0xff2bc000
94#define PMUCRU_SIZE SIZE_K(16)
95
96#define VOP_BASE 0xff460000
97#define VOP_SIZE SIZE_K(16)
98
99#define SERVER_MSCH_BASE 0xff530000
100#define SERVER_MSCH_SIZE SIZE_K(64)
101
102#define FIREWALL_DDR_BASE 0xff534000
103#define FIREWALL_DDR_SIZE SIZE_K(16)
104
105#define DDR_UPCTL_BASE 0xff600000
106#define DDR_UPCTL_SIZE SIZE_K(64)
107
108#define DDR_MNTR_BASE 0xff610000
109#define DDR_MNTR_SIZE SIZE_K(64)
110
111#define DDR_STDBY_BASE 0xff620000
112#define DDR_STDBY_SIZE SIZE_K(64)
113
114#define DDRGRF_BASE 0xff630000
115#define DDRGRF_SIZE SIZE_K(32)
116
117/**************************************************************************
118 * UART related constants
119 **************************************************************************/
120#define PX30_UART_BASE UART2_BASE
121#define PX30_BAUDRATE 1500000
122#define PX30_UART_CLOCK 24000000
123
124/******************************************************************************
125 * System counter frequency related constants
126 ******************************************************************************/
127#define SYS_COUNTER_FREQ_IN_TICKS 24000000
128#define SYS_COUNTER_FREQ_IN_MHZ 24
129
130/******************************************************************************
131 * GIC-400 & interrupt handling related constants
132 ******************************************************************************/
133
134/* Base rk_platform compatible GIC memory map */
135#define PX30_GICD_BASE (GIC400_BASE + 0x1000)
136#define PX30_GICC_BASE (GIC400_BASE + 0x2000)
137#define PX30_GICR_BASE 0 /* no GICR in GIC-400 */
138
139/******************************************************************************
140 * sgi, ppi
141 ******************************************************************************/
142#define RK_IRQ_SEC_PHY_TIMER 29
143
144#define RK_IRQ_SEC_SGI_0 8
145#define RK_IRQ_SEC_SGI_1 9
146#define RK_IRQ_SEC_SGI_2 10
147#define RK_IRQ_SEC_SGI_3 11
148#define RK_IRQ_SEC_SGI_4 12
149#define RK_IRQ_SEC_SGI_5 13
150#define RK_IRQ_SEC_SGI_6 14
151#define RK_IRQ_SEC_SGI_7 15
152
153/*
154 * Define a list of Group 0 interrupts.
155 */
156#define PLAT_RK_GICV2_G0_IRQS \
157 INTR_PROP_DESC(RK_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \
158 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), \
159 INTR_PROP_DESC(RK_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \
160 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL)
161
162#define SHARE_MEM_BASE 0x100000/* [1MB, 1MB+60K]*/
163#define SHARE_MEM_PAGE_NUM 15
164#define SHARE_MEM_SIZE SIZE_K(SHARE_MEM_PAGE_NUM * 4)
165
166#define DDR_PARAM_BASE 0x02000000
167#define DDR_PARAM_SIZE SIZE_K(4)
168
169#endif /* __PLAT_DEF_H__ */