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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Summer Qin93c812f2017-02-28 16:46:17 +00002 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <platform_def.h>
8
Dan Handley9df48042015-03-19 18:58:55 +00009#include <arch.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000010#include <plat/arm/common/plat_arm.h>
Dan Handley9df48042015-03-19 18:58:55 +000011
Soby Mathewfec4eb72015-07-01 16:16:20 +010012/*******************************************************************************
13 * This function validates an MPIDR by checking whether it falls within the
14 * acceptable bounds. An error code (-1) is returned if an incorrect mpidr
15 * is passed.
16 ******************************************************************************/
17int arm_check_mpidr(u_register_t mpidr)
Dan Handley9df48042015-03-19 18:58:55 +000018{
Soby Mathewfec4eb72015-07-01 16:16:20 +010019 unsigned int cluster_id, cpu_id;
Summer Qin93c812f2017-02-28 16:46:17 +000020 uint64_t valid_mask;
Soby Mathewfec4eb72015-07-01 16:16:20 +010021
Summer Qin93c812f2017-02-28 16:46:17 +000022#if ARM_PLAT_MT
23 unsigned int pe_id;
Soby Mathewfec4eb72015-07-01 16:16:20 +010024
Summer Qin93c812f2017-02-28 16:46:17 +000025 valid_mask = ~(MPIDR_AFFLVL_MASK |
26 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) |
27 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT));
28 cluster_id = (mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK;
29 cpu_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
30 pe_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
31#else
32 valid_mask = ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK);
Sathees Balya30952cc2018-09-27 14:41:02 +010033 cluster_id = (unsigned int) ((mpidr >> MPIDR_AFF1_SHIFT) &
34 MPIDR_AFFLVL_MASK);
35 cpu_id = (unsigned int) ((mpidr >> MPIDR_AFF0_SHIFT) &
36 MPIDR_AFFLVL_MASK);
Summer Qin93c812f2017-02-28 16:46:17 +000037#endif /* ARM_PLAT_MT */
38
39 mpidr &= MPIDR_AFFINITY_MASK;
Sathees Balya30952cc2018-09-27 14:41:02 +010040 if ((mpidr & valid_mask) != 0U)
Summer Qin93c812f2017-02-28 16:46:17 +000041 return -1;
Soby Mathewfec4eb72015-07-01 16:16:20 +010042
Soby Mathew47e43f22016-02-01 14:04:34 +000043 if (cluster_id >= PLAT_ARM_CLUSTER_COUNT)
Soby Mathewfec4eb72015-07-01 16:16:20 +010044 return -1;
45
46 /* Validate cpu_id by checking whether it represents a CPU in
47 one of the two clusters present on the platform. */
Soby Mathew47e43f22016-02-01 14:04:34 +000048 if (cpu_id >= plat_arm_get_cluster_core_count(mpidr))
Soby Mathewfec4eb72015-07-01 16:16:20 +010049 return -1;
50
Summer Qin93c812f2017-02-28 16:46:17 +000051#if ARM_PLAT_MT
52 if (pe_id >= plat_arm_get_cpu_pe_count(mpidr))
53 return -1;
54#endif /* ARM_PLAT_MT */
55
Soby Mathewfec4eb72015-07-01 16:16:20 +010056 return 0;
Dan Handley9df48042015-03-19 18:58:55 +000057}