| Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019, Intel Corporation. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef CLOCKMANAGER_H |
| 8 | #define CLOCKMANAGER_H |
| 9 | |
| 10 | #include "agilex_handoff.h" |
| 11 | |
| 12 | /* Clock Manager Registers */ |
| 13 | #define CLKMGR_OFFSET 0xffd10000 |
| 14 | |
| 15 | #define CLKMGR_CTRL 0x0 |
| 16 | #define CLKMGR_STAT 0x4 |
| 17 | #define CLKMGR_INTRCLR 0x14 |
| 18 | |
| 19 | /* Main PLL Group */ |
| 20 | #define CLKMGR_MAINPLL 0xffd10024 |
| 21 | #define CLKMGR_MAINPLL_EN 0x0 |
| 22 | #define CLKMGR_MAINPLL_BYPASS 0xc |
| 23 | #define CLKMGR_MAINPLL_MPUCLK 0x18 |
| 24 | #define CLKMGR_MAINPLL_NOCCLK 0x1c |
| 25 | #define CLKMGR_MAINPLL_NOCDIV 0x20 |
| 26 | #define CLKMGR_MAINPLL_PLLGLOB 0x24 |
| 27 | #define CLKMGR_MAINPLL_FDBCK 0x28 |
| 28 | #define CLKMGR_MAINPLL_MEM 0x2c |
| 29 | #define CLKMGR_MAINPLL_MEMSTAT 0x30 |
| 30 | #define CLKMGR_MAINPLL_PLLC0 0x34 |
| 31 | #define CLKMGR_MAINPLL_PLLC1 0x38 |
| 32 | #define CLKMGR_MAINPLL_VCOCALIB 0x3c |
| 33 | #define CLKMGR_MAINPLL_PLLC2 0x40 |
| 34 | #define CLKMGR_MAINPLL_PLLC3 0x44 |
| 35 | #define CLKMGR_MAINPLL_PLLM 0x48 |
| 36 | |
| 37 | /* Peripheral PLL Group */ |
| 38 | #define CLKMGR_PERPLL 0xffd1007c |
| 39 | #define CLKMGR_PERPLL_EN 0x0 |
| 40 | #define CLKMGR_PERPLL_BYPASS 0xc |
| 41 | #define CLKMGR_PERPLL_EMACCTL 0x18 |
| 42 | #define CLKMGR_PERPLL_GPIODIV 0x1c |
| 43 | #define CLKMGR_PERPLL_PLLGLOB 0x20 |
| 44 | #define CLKMGR_PERPLL_FDBCK 0x24 |
| 45 | #define CLKMGR_PERPLL_MEM 0x28 |
| 46 | #define CLKMGR_PERPLL_MEMSTAT 0x2c |
| 47 | #define CLKMGR_PERPLL_PLLC0 0x30 |
| 48 | #define CLKMGR_PERPLL_PLLC1 0x34 |
| 49 | #define CLKMGR_PERPLL_VCOCALIB 0x38 |
| 50 | #define CLKMGR_PERPLL_PLLC2 0x3c |
| 51 | #define CLKMGR_PERPLL_PLLC3 0x40 |
| 52 | #define CLKMGR_PERPLL_PLLM 0x44 |
| 53 | |
| 54 | /* Altera Group */ |
| 55 | #define CLKMGR_ALTERA 0xffd100d0 |
| 56 | #define CLKMGR_ALTERA_JTAG 0x0 |
| 57 | #define CLKMGR_ALTERA_EMACACTR 0x4 |
| 58 | #define CLKMGR_ALTERA_EMACBCTR 0x8 |
| 59 | #define CLKMGR_ALTERA_EMACPTPCTR 0xc |
| 60 | #define CLKMGR_ALTERA_GPIODBCTR 0x10 |
| 61 | #define CLKMGR_ALTERA_SDMMCCTR 0x14 |
| 62 | #define CLKMGR_ALTERA_S2FUSER0CTR 0x18 |
| 63 | #define CLKMGR_ALTERA_S2FUSER1CTR 0x1c |
| 64 | #define CLKMGR_ALTERA_PSIREFCTR 0x20 |
| 65 | #define CLKMGR_ALTERA_EXTCNTRST 0x24 |
| 66 | |
| 67 | /* Membus */ |
| 68 | #define CLKMGR_MEM_REQ BIT(24) |
| 69 | #define CLKMGR_MEM_WR BIT(25) |
| 70 | #define CLKMGR_MEM_ERR BIT(26) |
| 71 | #define CLKMGR_MEM_WDAT_OFFSET 16 |
| 72 | #define CLKMGR_MEM_ADDR 0x4027 |
| 73 | #define CLKMGR_MEM_WDAT 0x80 |
| 74 | |
| 75 | /* Clock Manager Macros */ |
| 76 | #define CLKMGR_CTRL_BOOTMODE_SET_MSK 0x00000001 |
| 77 | #define CLKMGR_STAT_BUSY_E_BUSY 0x1 |
| 78 | #define CLKMGR_STAT_BUSY(x) (((x) & 0x00000001) >> 0) |
| 79 | #define CLKMGR_STAT_MAINPLLLOCKED(x) (((x) & 0x00000100) >> 8) |
| 80 | #define CLKMGR_STAT_PERPLLLOCKED(x) (((x) & 0x00010000) >> 16) |
| 81 | #define CLKMGR_INTRCLR_MAINLOCKLOST_SET_MSK 0x00000004 |
| 82 | #define CLKMGR_INTRCLR_PERLOCKLOST_SET_MSK 0x00000008 |
| 83 | |
| 84 | /* Main PLL Macros */ |
| 85 | #define CLKMGR_MAINPLL_EN_RESET 0x000000ff |
| 86 | #define CLKMGR_MAINPLL_PLLM_MDIV(x) ((x) & 0x000003ff) |
| 87 | #define CLKMGR_MAINPLL_PLLGLOB_PD_SET_MSK 0x00000001 |
| 88 | #define CLKMGR_MAINPLL_PLLGLOB_RST_SET_MSK 0x00000002 |
| 89 | |
| 90 | #define CLKMGR_MAINPLL_PLLGLOB_REFCLKDIV(x) (((x) & 0x00003f00) >> 8) |
| 91 | #define CLKMGR_MAINPLL_PLLGLOB_AREFCLKDIV(x) (((x) & 0x00000f00) >> 8) |
| 92 | #define CLKMGR_MAINPLL_PLLGLOB_DREFCLKDIV(x) (((x) & 0x00003000) >> 12) |
| 93 | |
| 94 | #define CLKMGR_MAINPLL_PLLGLOB_PSRC(x) (((x) & 0x00030000) >> 16) |
| 95 | #define CLKMGR_MAINPLL_PLLGLOB_PSRC_EOSC1 0x0 |
| 96 | #define CLKMGR_MAINPLL_PLLGLOB_PSRC_INTOSC 0x1 |
| 97 | #define CLKMGR_MAINPLL_PLLGLOB_PSRC_F2S 0x2 |
| 98 | #define CLKMGR_MAINPLL_VCOCALIB_HSCNT_SET(x) (((x) << 0) & 0x000003ff) |
| 99 | #define CLKMGR_MAINPLL_VCOCALIB_MSCNT_SET(x) (((x) << 16) & 0x00ff0000) |
| 100 | |
| 101 | /* Peripheral PLL Macros */ |
| 102 | #define CLKMGR_PERPLL_EN_RESET 0x00000fff |
| 103 | #define CLKMGR_PERPLL_PLLM_MDIV(x) ((x) & 0x000003ff) |
| 104 | #define CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x0000ffff) |
| 105 | #define CLKMGR_PERPLL_PLLGLOB_PD_SET_MSK 0x00000001 |
| 106 | |
| 107 | #define CLKMGR_PERPLL_PLLGLOB_REFCLKDIV(x) (((x) & 0x00003f00) >> 8) |
| 108 | #define CLKMGR_PERPLL_PLLGLOB_AREFCLKDIV(x) (((x) & 0x00000f00) >> 8) |
| 109 | #define CLKMGR_PERPLL_PLLGLOB_DREFCLKDIV(x) (((x) & 0x00003000) >> 12) |
| 110 | |
| 111 | #define CLKMGR_PERPLL_PLLGLOB_RST_SET_MSK 0x00000002 |
| 112 | #define CLKMGR_PERPLL_VCOCALIB_HSCNT_SET(x) (((x) << 0) & 0x000003ff) |
| 113 | #define CLKMGR_PERPLL_VCOCALIB_MSCNT_SET(x) (((x) << 16) & 0x00ff0000) |
| 114 | |
| 115 | /* Altera Macros */ |
| 116 | #define CLKMGR_ALTERA_EXTCNTRST_RESET 0xff |
| 117 | |
| 118 | |
| 119 | typedef struct { |
| 120 | uint32_t clk_freq_of_eosc1; |
| 121 | uint32_t clk_freq_of_f2h_free; |
| 122 | uint32_t clk_freq_of_cb_intosc_ls; |
| 123 | } CLOCK_SOURCE_CONFIG; |
| 124 | |
| 125 | void config_clkmgr_handoff(handoff *hoff_ptr); |
| 126 | int get_wdt_clk(handoff *hoff_ptr); |
| 127 | |
| 128 | #endif |