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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Roberto Vargas2b36b152018-02-12 12:36:17 +00002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6
Dan Handley9df48042015-03-19 18:58:55 +00007#include <platform_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008
9#include <drivers/arm/nic_400.h>
10#include <lib/mmio.h>
11
Roberto Vargas2b36b152018-02-12 12:36:17 +000012#include <soc_css.h>
Dan Handley9df48042015-03-19 18:58:55 +000013
Dan Handley9df48042015-03-19 18:58:55 +000014void soc_css_init_nic400(void)
15{
16 /*
17 * NIC-400 Access Control Initialization
18 *
19 * Define access privileges by setting each corresponding bit to:
20 * 0 = Secure access only
21 * 1 = Non-secure access allowed
22 */
23
24 /*
25 * Allow non-secure access to some SOC regions, excluding UART1, which
Alexei Fedorove9ab9052017-05-25 15:57:18 +010026 * remains secure (unless CSS_NON_SECURE_UART is set).
Dan Handley9df48042015-03-19 18:58:55 +000027 * Note: This is the NIC-400 device on the SOC
28 */
29 mmio_write_32(SOC_CSS_NIC400_BASE +
30 NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_USB_EHCI), ~0);
31 mmio_write_32(SOC_CSS_NIC400_BASE +
32 NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_TLX_MASTER), ~0);
33 mmio_write_32(SOC_CSS_NIC400_BASE +
34 NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_USB_OHCI), ~0);
35 mmio_write_32(SOC_CSS_NIC400_BASE +
36 NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_PL354_SMC), ~0);
37 mmio_write_32(SOC_CSS_NIC400_BASE +
38 NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_APB4_BRIDGE), ~0);
Alexei Fedorove9ab9052017-05-25 15:57:18 +010039#if CSS_NON_SECURE_UART
40 /* Configure UART for non-secure access */
41 mmio_write_32(SOC_CSS_NIC400_BASE +
42 NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_BOOTSEC_BRIDGE), ~0);
43#else
Dan Handley9df48042015-03-19 18:58:55 +000044 mmio_write_32(SOC_CSS_NIC400_BASE +
45 NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_BOOTSEC_BRIDGE),
46 ~SOC_CSS_NIC400_BOOTSEC_BRIDGE_UART1);
Alexei Fedorove9ab9052017-05-25 15:57:18 +010047#endif /* CSS_NON_SECURE_UART */
Dan Handley9df48042015-03-19 18:58:55 +000048
Dan Handley9df48042015-03-19 18:58:55 +000049}
50
51
52#define PCIE_SECURE_REG 0x3000
53/* Mask uses REG and MEM access bits */
54#define PCIE_SEC_ACCESS_MASK ((1 << 0) | (1 << 1))
55
56void soc_css_init_pcie(void)
57{
58#if !PLAT_juno
59 /*
60 * Do not initialize PCIe in emulator environment.
61 * Platform ID register not supported on Juno
62 */
63 if (BOARD_CSS_GET_PLAT_TYPE(BOARD_CSS_PLAT_ID_REG_ADDR) ==
64 BOARD_CSS_PLAT_TYPE_EMULATOR)
65 return;
66#endif /* PLAT_juno */
67
68 /*
69 * PCIE Root Complex Security settings to enable non-secure
70 * access to config registers.
71 */
72 mmio_write_32(SOC_CSS_PCIE_CONTROL_BASE + PCIE_SECURE_REG,
73 PCIE_SEC_ACCESS_MASK);
74}