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Nariman Poushin0ece80f2018-02-26 06:52:04 +00001/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <assert.h>
8
9#include <platform_def.h>
10
11#include <common/bl_common.h>
12#include <common/debug.h>
13#include <drivers/arm/ccn.h>
14#include <plat/common/platform.h>
15#include <services/secure_partition.h>
16
Nariman Poushin0ece80f2018-02-26 06:52:04 +000017#include <arm_def.h>
Sughosh Ganue1579e02018-05-16 17:19:56 +053018#include <arm_spm_def.h>
Nariman Poushin0ece80f2018-02-26 06:52:04 +000019#include <plat_arm.h>
Nariman Poushin0ece80f2018-02-26 06:52:04 +000020#include "../../../../bl1/bl1_private.h"
21
22#if USE_COHERENT_MEM
23/*
24 * The next 2 constants identify the extents of the coherent memory region.
25 * These addresses are used by the MMU setup code and therefore they must be
26 * page-aligned. It is the responsibility of the linker script to ensure that
27 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
28 * refer to page-aligned addresses.
29 */
30#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
31#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
32#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
33#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
34
35#define BL31_COHERENT_RAM_BASE (uintptr_t)(&__COHERENT_RAM_START__)
36#define BL31_COHERENT_RAM_LIMIT (uintptr_t)(&__COHERENT_RAM_END__)
37#endif
38
39#define SGI_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\
40 V2M_FLASH0_SIZE, \
41 MT_DEVICE | MT_RO | MT_SECURE)
42/*
43 * Table of regions for different BL stages to map using the MMU.
44 * This doesn't include Trusted RAM as the 'mem_layout' argument passed to
45 * arm_configure_mmu_elx() will give the available subset of that.
46 *
47 * Replace or extend the below regions as required
48 */
49#if IMAGE_BL1
50const mmap_region_t plat_arm_mmap[] = {
51 ARM_MAP_SHARED_RAM,
52 SGI_MAP_FLASH0_RO,
53 CSS_SGI_MAP_DEVICE,
54 SOC_CSS_MAP_DEVICE,
55 {0}
56};
57#endif
58#if IMAGE_BL2
59const mmap_region_t plat_arm_mmap[] = {
60 ARM_MAP_SHARED_RAM,
61 SGI_MAP_FLASH0_RO,
62 CSS_SGI_MAP_DEVICE,
63 SOC_CSS_MAP_DEVICE,
64 ARM_MAP_NS_DRAM1,
65#if ARM_BL31_IN_DRAM
66 ARM_MAP_BL31_SEC_DRAM,
67#endif
Sughosh Ganue1579e02018-05-16 17:19:56 +053068#if ENABLE_SPM
69 ARM_SP_IMAGE_MMAP,
70#endif
Antonio Nino Diaz9b759862018-09-25 11:38:18 +010071#if TRUSTED_BOARD_BOOT && !BL2_AT_EL3
John Tsichritzis0c6ee742018-08-22 12:36:37 +010072 ARM_MAP_BL1_RW,
73#endif
Nariman Poushin0ece80f2018-02-26 06:52:04 +000074 {0}
75};
76#endif
77#if IMAGE_BL31
78const mmap_region_t plat_arm_mmap[] = {
79 ARM_MAP_SHARED_RAM,
80 V2M_MAP_IOFPGA,
81 CSS_SGI_MAP_DEVICE,
82 SOC_CSS_MAP_DEVICE,
Sughosh Ganue1579e02018-05-16 17:19:56 +053083#if ENABLE_SPM
84 ARM_SPM_BUF_EL3_MMAP,
85#endif
Nariman Poushin0ece80f2018-02-26 06:52:04 +000086 {0}
87};
Sughosh Ganue1579e02018-05-16 17:19:56 +053088
89#if ENABLE_SPM && defined(IMAGE_BL31)
90const mmap_region_t plat_arm_secure_partition_mmap[] = {
91 PLAT_ARM_SECURE_MAP_DEVICE,
92 ARM_SP_IMAGE_MMAP,
93 ARM_SP_IMAGE_NS_BUF_MMAP,
Sughosh Ganu70661cf2018-05-16 17:26:40 +053094 ARM_SP_CPER_BUF_MMAP,
Sughosh Ganue1579e02018-05-16 17:19:56 +053095 ARM_SP_IMAGE_RW_MMAP,
96 ARM_SPM_BUF_EL0_MMAP,
97 {0}
98};
99#endif /* ENABLE_SPM && defined(IMAGE_BL31) */
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000100#endif
101
102ARM_CASSERT_MMAP
Sughosh Ganue1579e02018-05-16 17:19:56 +0530103
104#if ENABLE_SPM && defined(IMAGE_BL31)
105/*
106 * Boot information passed to a secure partition during initialisation. Linear
107 * indices in MP information will be filled at runtime.
108 */
109static secure_partition_mp_info_t sp_mp_info[] = {
110 [0] = {0x81000000, 0},
111 [1] = {0x81000100, 0},
112 [2] = {0x81000200, 0},
113 [3] = {0x81000300, 0},
114 [4] = {0x81010000, 0},
115 [5] = {0x81010100, 0},
116 [6] = {0x81010200, 0},
117 [7] = {0x81010300, 0},
118};
119
120const secure_partition_boot_info_t plat_arm_secure_partition_boot_info = {
121 .h.type = PARAM_SP_IMAGE_BOOT_INFO,
122 .h.version = VERSION_1,
123 .h.size = sizeof(secure_partition_boot_info_t),
124 .h.attr = 0,
125 .sp_mem_base = ARM_SP_IMAGE_BASE,
126 .sp_mem_limit = ARM_SP_IMAGE_LIMIT,
127 .sp_image_base = ARM_SP_IMAGE_BASE,
128 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
129 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE,
130 .sp_ns_comm_buf_base = ARM_SP_IMAGE_NS_BUF_BASE,
131 .sp_shared_buf_base = PLAT_SPM_BUF_BASE,
132 .sp_image_size = ARM_SP_IMAGE_SIZE,
133 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
134 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE,
135 .sp_ns_comm_buf_size = ARM_SP_IMAGE_NS_BUF_SIZE,
136 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
137 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS,
138 .num_cpus = PLATFORM_CORE_COUNT,
139 .mp_info = &sp_mp_info[0],
140};
141
142const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
143{
144 return plat_arm_secure_partition_mmap;
145}
146
147const struct secure_partition_boot_info *plat_get_secure_partition_boot_info(
148 void *cookie)
149{
150 return &plat_arm_secure_partition_boot_info;
151}
152#endif /* ENABLE_SPM && defined(IMAGE_BL31) */
John Tsichritzis0c6ee742018-08-22 12:36:37 +0100153
Antonio Nino Diaz9b759862018-09-25 11:38:18 +0100154#if TRUSTED_BOARD_BOOT
John Tsichritzis0c6ee742018-08-22 12:36:37 +0100155int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
156{
157 assert(heap_addr != NULL);
158 assert(heap_size != NULL);
159
160 return arm_get_mbedtls_heap(heap_addr, heap_size);
161}
162#endif