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Etienne Carriere911de8c2018-02-02 13:23:22 +01001/*
Ambroise Vincent962109f2019-03-27 13:48:15 +00002 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
Etienne Carriere911de8c2018-02-02 13:23:22 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <assert_macros.S>
10#include <platform_def.h>
11
12 .globl plat_my_core_pos
13 .globl plat_get_my_entrypoint
14 .globl platform_mem_init
15 .globl plat_qemu_calc_core_pos
16 .globl plat_crash_console_init
17 .globl plat_crash_console_putc
Ambroise Vincent962109f2019-03-27 13:48:15 +000018 .globl plat_crash_console_flush
Etienne Carriere911de8c2018-02-02 13:23:22 +010019 .globl plat_secondary_cold_boot_setup
20 .globl plat_get_my_entrypoint
21 .globl plat_is_my_cpu_primary
22
23
24func plat_my_core_pos
25 ldcopr r0, MPIDR
26 b plat_qemu_calc_core_pos
27endfunc plat_my_core_pos
28
29/*
30 * unsigned int plat_qemu_calc_core_pos(u_register_t mpidr);
31 * With this function: CorePos = (ClusterId * 4) + CoreId
32 */
33func plat_qemu_calc_core_pos
34 and r1, r0, #MPIDR_CPU_MASK
35 and r0, r0, #MPIDR_CLUSTER_MASK
36 add r0, r1, r0, LSR #6
37 bx lr
38endfunc plat_qemu_calc_core_pos
39
40 /* -----------------------------------------------------
41 * unsigned int plat_is_my_cpu_primary (void);
42 *
43 * Find out whether the current cpu is the primary
44 * cpu.
45 * -----------------------------------------------------
46 */
47func plat_is_my_cpu_primary
48 ldcopr r0, MPIDR
49 ldr r1, =(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
50 and r0, r1
51 cmp r0, #QEMU_PRIMARY_CPU
52 moveq r0, #1
53 movne r0, #0
54 bx lr
55endfunc plat_is_my_cpu_primary
56
57 /* -----------------------------------------------------
58 * void plat_secondary_cold_boot_setup (void);
59 *
60 * This function performs any platform specific actions
61 * needed for a secondary cpu after a cold reset e.g
62 * mark the cpu's presence, mechanism to place it in a
63 * holding pen etc.
64 * -----------------------------------------------------
65 */
66func plat_secondary_cold_boot_setup
67 /* Calculate address of our hold entry */
68 bl plat_my_core_pos
69 lsl r0, r0, #PLAT_QEMU_HOLD_ENTRY_SHIFT
70 mov_imm r2, PLAT_QEMU_HOLD_BASE
71
72 /* Wait until we have a go */
73poll_mailbox:
74 ldr r1, [r2, r0]
75 cmp r1, #0
76 beq 1f
77 mov_imm r0, PLAT_QEMU_TRUSTED_MAILBOX_BASE
78 ldr r1, [r0]
79 bx r1
801:
81 wfe
82 b poll_mailbox
83endfunc plat_secondary_cold_boot_setup
84
85func plat_get_my_entrypoint
86 /* TODO support warm boot */
87 mov r0, #0
88 bx lr
89endfunc plat_get_my_entrypoint
90
91func platform_mem_init
92 bx lr
93endfunc platform_mem_init
94
95 /* ---------------------------------------------
96 * int plat_crash_console_init(void)
97 * Function to initialize the crash console
98 * without a C Runtime to print crash report.
99 * Clobber list : x0, x1, x2
100 * ---------------------------------------------
101 */
102func plat_crash_console_init
103 mov_imm r0, PLAT_QEMU_CRASH_UART_BASE
104 mov_imm r1, PLAT_QEMU_CRASH_UART_CLK_IN_HZ
105 mov_imm r2, PLAT_QEMU_CONSOLE_BAUDRATE
106 b console_core_init
107endfunc plat_crash_console_init
108
109 /* ---------------------------------------------
110 * int plat_crash_console_putc(int c)
111 * Function to print a character on the crash
112 * console without a C Runtime.
113 * Clobber list : x1, x2
114 * ---------------------------------------------
115 */
116func plat_crash_console_putc
117 mov_imm r1, PLAT_QEMU_CRASH_UART_BASE
118 b console_core_putc
119endfunc plat_crash_console_putc
120
Ambroise Vincent962109f2019-03-27 13:48:15 +0000121 /* ---------------------------------------------
122 * int plat_crash_console_flush(int c)
123 * Function to force a write of all buffered
124 * data that hasn't been output.
125 * Out : return -1 on error else return 0.
126 * Clobber list : x0, x1
127 * ---------------------------------------------
128 */
129func plat_crash_console_flush
130 mov_imm r0, PLAT_QEMU_CRASH_UART_BASE
131 b console_core_flush
132endfunc plat_crash_console_flush
133