| Andre Przywara | 6228e43 | 2020-09-16 17:13:33 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2020, ARM Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | * |
| 6 | * Linker script for the Arm Ltd. FPGA boards to generate an ELF file that |
| 7 | * contains the ROM trampoline, BL31 and the DTB. |
| 8 | * |
| 9 | * This allows to pass just one file to the uploader tool, and automatically |
| 10 | * provides the correct load addresses. |
| 11 | */ |
| 12 | |
| 13 | #include <platform_def.h> |
| 14 | |
| 15 | OUTPUT_FORMAT("elf64-littleaarch64") |
| 16 | OUTPUT_ARCH(aarch64) |
| 17 | |
| 18 | INPUT(./bl31/bl31.elf) |
| 19 | INPUT(./rom_trampoline.o) |
| 20 | |
| 21 | TARGET(binary) |
| 22 | INPUT(./fdts/arm_fpga.dtb) |
| 23 | |
| 24 | ENTRY(_start) |
| 25 | |
| 26 | SECTIONS |
| 27 | { |
| 28 | .rom (0x0): { |
| 29 | *rom_trampoline.o(.text*) |
| 30 | KEEP(*(.rom)) |
| 31 | } |
| 32 | |
| 33 | .bl31 (BL31_BASE): { |
| 34 | ASSERT(. == ALIGN(PAGE_SIZE), "BL31_BASE is not page aligned"); |
| 35 | *bl31.elf(.text* .data* .rodata* ro* .bss*) |
| 36 | *bl31.elf(.stack) |
| 37 | } |
| 38 | |
| 39 | .dtb (FPGA_PRELOADED_DTB_BASE): { |
| 40 | ASSERT(. == ALIGN(8), "DTB address is not 8-byte aligned"); |
| 41 | *arm_fpga.dtb |
| 42 | } |
| 43 | |
| 44 | /DISCARD/ : { *(.debug_*) } |
| 45 | /DISCARD/ : { *(.note*) } |
| 46 | /DISCARD/ : { *(.comment*) } |
| 47 | } |