Bai Ping | 06e325e | 2018-10-28 00:12:34 +0800 | [diff] [blame] | 1 | /* |
Jimmy Brisson | 39f9eee | 2020-08-05 13:44:05 -0500 | [diff] [blame] | 2 | * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. |
Bai Ping | 06e325e | 2018-10-28 00:12:34 +0800 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
Bai Ping | 06e325e | 2018-10-28 00:12:34 +0800 | [diff] [blame] | 9 | #include <console_macros.S> |
| 10 | #include <assert_macros.S> |
| 11 | #include "imx_uart.h" |
| 12 | |
| 13 | #define URXD 0x0 /* Receiver Register */ |
| 14 | #define UTXD 0x40 /* Transmitter Register */ |
Loic Poulain | 311b33d | 2023-01-11 16:08:48 +0100 | [diff] [blame] | 15 | #define USR2 0x98 /* UART Status Register 2 */ |
Bai Ping | 06e325e | 2018-10-28 00:12:34 +0800 | [diff] [blame] | 16 | #define UTS 0xb4 /* UART Test Register (mx31) */ |
| 17 | #define URXD_RX_DATA (0xFF) |
| 18 | |
Anson Huang | 1fc11bd | 2019-01-15 14:27:10 +0800 | [diff] [blame] | 19 | .globl console_imx_uart_register |
| 20 | .globl console_imx_uart_init |
| 21 | .globl console_imx_uart_putc |
| 22 | .globl console_imx_uart_getc |
| 23 | .globl console_imx_uart_flush |
Bai Ping | 06e325e | 2018-10-28 00:12:34 +0800 | [diff] [blame] | 24 | |
| 25 | func console_imx_uart_register |
| 26 | mov x7, x30 |
| 27 | mov x6, x3 |
| 28 | cbz x6, register_fail |
Andre Przywara | ab26920 | 2020-03-05 13:56:56 +0000 | [diff] [blame] | 29 | str x0, [x6, #CONSOLE_T_BASE] |
Bai Ping | 06e325e | 2018-10-28 00:12:34 +0800 | [diff] [blame] | 30 | |
| 31 | bl console_imx_uart_init |
| 32 | cbz x0, register_fail |
| 33 | |
| 34 | mov x0, x6 |
| 35 | mov x30, x7 |
Anson Huang | 1fc11bd | 2019-01-15 14:27:10 +0800 | [diff] [blame] | 36 | finish_console_register imx_uart putc=1, getc=1, flush=1 |
Bai Ping | 06e325e | 2018-10-28 00:12:34 +0800 | [diff] [blame] | 37 | |
| 38 | register_fail: |
| 39 | ret x7 |
| 40 | endfunc console_imx_uart_register |
| 41 | |
| 42 | func console_imx_uart_init |
| 43 | mov w0, #1 |
| 44 | ret |
| 45 | endfunc console_imx_uart_init |
| 46 | |
| 47 | func console_imx_uart_putc |
Andre Przywara | ab26920 | 2020-03-05 13:56:56 +0000 | [diff] [blame] | 48 | ldr x1, [x1, #CONSOLE_T_BASE] |
Bai Ping | 06e325e | 2018-10-28 00:12:34 +0800 | [diff] [blame] | 49 | cbz x1, putc_error |
| 50 | |
| 51 | /* Prepare '\r' to '\n' */ |
| 52 | cmp w0, #0xA |
| 53 | b.ne 2f |
| 54 | 1: |
| 55 | /* Check if the transmit FIFO is full */ |
| 56 | ldr w2, [x1, #UTS] |
Loic Poulain | 311b33d | 2023-01-11 16:08:48 +0100 | [diff] [blame] | 57 | tbnz w2, #4, 1b |
Bai Ping | 06e325e | 2018-10-28 00:12:34 +0800 | [diff] [blame] | 58 | mov w2, #0xD |
| 59 | str w2, [x1, #UTXD] |
| 60 | 2: |
| 61 | /* Check if the transmit FIFO is full */ |
| 62 | ldr w2, [x1, #UTS] |
Loic Poulain | 311b33d | 2023-01-11 16:08:48 +0100 | [diff] [blame] | 63 | tbnz w2, #4, 2b |
Bai Ping | 06e325e | 2018-10-28 00:12:34 +0800 | [diff] [blame] | 64 | str w0, [x1, #UTXD] |
| 65 | ret |
| 66 | putc_error: |
| 67 | mov w0, #-1 |
| 68 | ret |
| 69 | endfunc console_imx_uart_putc |
| 70 | |
| 71 | func console_imx_uart_getc |
Andre Przywara | ab26920 | 2020-03-05 13:56:56 +0000 | [diff] [blame] | 72 | ldr x0, [x0, #CONSOLE_T_BASE] |
Bai Ping | 06e325e | 2018-10-28 00:12:34 +0800 | [diff] [blame] | 73 | cbz x0, getc_error |
| 74 | 1: |
| 75 | ldr w1, [x0, #UTS] |
| 76 | tbnz w1, #5, 1b |
| 77 | |
| 78 | ldr w1, [x0, #URXD] |
| 79 | and w0, w1, #URXD_RX_DATA |
| 80 | |
| 81 | ret |
| 82 | getc_error: |
| 83 | mov w0, #-1 |
| 84 | ret |
| 85 | endfunc console_imx_uart_getc |
Anson Huang | 1fc11bd | 2019-01-15 14:27:10 +0800 | [diff] [blame] | 86 | |
| 87 | func console_imx_uart_flush |
Loic Poulain | 311b33d | 2023-01-11 16:08:48 +0100 | [diff] [blame] | 88 | ldr x0, [x0, #CONSOLE_T_BASE] |
| 89 | cbz x0, flush_exit |
| 90 | 1: |
| 91 | /* Wait for the transmit complete bit */ |
| 92 | ldr w1, [x0, #USR2] |
| 93 | tbz w1, #3, 1b |
| 94 | |
| 95 | flush_exit: |
Anson Huang | 1fc11bd | 2019-01-15 14:27:10 +0800 | [diff] [blame] | 96 | ret |
| 97 | endfunc console_imx_uart_flush |