blob: 3336b62d9cd16829c912196affb32a906f895da0 [file] [log] [blame]
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +00001/*
2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __XLAT_TABLES_ARCH_H__
32#define __XLAT_TABLES_ARCH_H__
33
34#include <arch.h>
35#include <platform_def.h>
36#include <xlat_tables_defs.h>
37
38/*
39 * In AArch64 state, the MMU may support 4 KB, 16 KB and 64 KB page
40 * granularity. For 4KB granularity, a level 0 table descriptor doesn't support
41 * block translation. For 16KB, the same thing happens to levels 0 and 1. For
42 * 64KB, same for level 1. See section D4.3.1 of the ARMv8-A Architecture
43 * Reference Manual (DDI 0487A.k) for more information.
44 *
45 * The define below specifies the first table level that allows block
46 * descriptors.
47 */
48
49#if PAGE_SIZE == (4*1024) /* 4KB */
50# define MIN_LVL_BLOCK_DESC 1
51#else /* 16KB or 64KB */
52# define MIN_LVL_BLOCK_DESC 2
53#endif
54
55/*
56 * Each platform can define the size of the virtual address space, which is
57 * defined in PLAT_VIRT_ADDR_SPACE_SIZE. TCR.TxSZ is calculated as 64 minus the
58 * width of said address space. The value of TCR.TxSZ must be in the range 16
59 * to 39 [1], which means that the virtual address space width must be in the
60 * range 48 to 25 bits.
61 *
62 * Here we calculate the initial lookup level from the value of
63 * PLAT_VIRT_ADDR_SPACE_SIZE. For a 4 KB page size, level 0 supports virtual
64 * address spaces of widths 48 to 40 bits, level 1 from 39 to 31, and level 2
65 * from 30 to 25. Wider or narrower address spaces are not supported. As a
66 * result, level 3 cannot be used as initial lookup level with 4 KB
67 * granularity. [2]
68 *
69 * For example, for a 35-bit address space (i.e. PLAT_VIRT_ADDR_SPACE_SIZE ==
70 * 1 << 35), TCR.TxSZ will be programmed to (64 - 35) = 29. According to Table
71 * D4-11 in the ARM ARM, the initial lookup level for an address space like
72 * that is 1.
73 *
74 * See the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more
75 * information:
76 * [1] Page 1730: 'Input address size', 'For all translation stages'.
77 * [2] Section D4.2.5
78 */
79
80#if PLAT_VIRT_ADDR_SPACE_SIZE > (1ULL << (64 - TCR_TxSZ_MIN))
81
82# error "PLAT_VIRT_ADDR_SPACE_SIZE is too big."
83
84#elif PLAT_VIRT_ADDR_SPACE_SIZE > (1ULL << L0_XLAT_ADDRESS_SHIFT)
85
86# define XLAT_TABLE_LEVEL_BASE 0
87# define NUM_BASE_LEVEL_ENTRIES \
88 (PLAT_VIRT_ADDR_SPACE_SIZE >> L0_XLAT_ADDRESS_SHIFT)
89
90#elif PLAT_VIRT_ADDR_SPACE_SIZE > (1 << L1_XLAT_ADDRESS_SHIFT)
91
92# define XLAT_TABLE_LEVEL_BASE 1
93# define NUM_BASE_LEVEL_ENTRIES \
94 (PLAT_VIRT_ADDR_SPACE_SIZE >> L1_XLAT_ADDRESS_SHIFT)
95
96#elif PLAT_VIRT_ADDR_SPACE_SIZE >= (1 << (64 - TCR_TxSZ_MAX))
97
98# define XLAT_TABLE_LEVEL_BASE 2
99# define NUM_BASE_LEVEL_ENTRIES \
100 (PLAT_VIRT_ADDR_SPACE_SIZE >> L2_XLAT_ADDRESS_SHIFT)
101
102#else
103
104# error "PLAT_VIRT_ADDR_SPACE_SIZE is too small."
105
106#endif
107
108#endif /* __XLAT_TABLES_ARCH_H__ */