Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Dan Handley | e83b0ca | 2014-01-14 18:17:09 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 31 | #include <arch.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 32 | #include <asm_macros.S> |
| 33 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 34 | .globl flush_dcache_range |
Achin Gupta | e9c4a64 | 2015-09-11 16:03:13 +0100 | [diff] [blame] | 35 | .globl clean_dcache_range |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 36 | .globl inv_dcache_range |
| 37 | .globl dcsw_op_louis |
| 38 | .globl dcsw_op_all |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 39 | .globl dcsw_op_level1 |
| 40 | .globl dcsw_op_level2 |
| 41 | .globl dcsw_op_level3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 42 | |
Achin Gupta | e9c4a64 | 2015-09-11 16:03:13 +0100 | [diff] [blame] | 43 | /* |
| 44 | * This macro can be used for implementing various data cache operations `op` |
| 45 | */ |
| 46 | .macro do_dcache_maintenance_by_mva op |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 47 | dcache_line_size x2, x3 |
| 48 | add x1, x0, x1 |
| 49 | sub x3, x2, #1 |
| 50 | bic x0, x0, x3 |
Achin Gupta | e9c4a64 | 2015-09-11 16:03:13 +0100 | [diff] [blame] | 51 | loop_\op: |
| 52 | dc \op, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 53 | add x0, x0, x2 |
| 54 | cmp x0, x1 |
Achin Gupta | e9c4a64 | 2015-09-11 16:03:13 +0100 | [diff] [blame] | 55 | b.lo loop_\op |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 56 | dsb sy |
| 57 | ret |
Achin Gupta | e9c4a64 | 2015-09-11 16:03:13 +0100 | [diff] [blame] | 58 | .endm |
| 59 | /* ------------------------------------------ |
| 60 | * Clean+Invalidate from base address till |
| 61 | * size. 'x0' = addr, 'x1' = size |
| 62 | * ------------------------------------------ |
| 63 | */ |
| 64 | func flush_dcache_range |
| 65 | do_dcache_maintenance_by_mva civac |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 66 | endfunc flush_dcache_range |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 67 | |
Achin Gupta | e9c4a64 | 2015-09-11 16:03:13 +0100 | [diff] [blame] | 68 | /* ------------------------------------------ |
| 69 | * Clean from base address till size. |
| 70 | * 'x0' = addr, 'x1' = size |
| 71 | * ------------------------------------------ |
| 72 | */ |
| 73 | func clean_dcache_range |
| 74 | do_dcache_maintenance_by_mva cvac |
| 75 | endfunc clean_dcache_range |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 76 | |
| 77 | /* ------------------------------------------ |
| 78 | * Invalidate from base address till |
| 79 | * size. 'x0' = addr, 'x1' = size |
| 80 | * ------------------------------------------ |
| 81 | */ |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 82 | func inv_dcache_range |
Achin Gupta | e9c4a64 | 2015-09-11 16:03:13 +0100 | [diff] [blame] | 83 | do_dcache_maintenance_by_mva ivac |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 84 | endfunc inv_dcache_range |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 85 | |
| 86 | |
Andrew Thoelke | 6a5b3a4 | 2014-04-25 10:49:30 +0100 | [diff] [blame] | 87 | /* --------------------------------------------------------------- |
| 88 | * Data cache operations by set/way to the level specified |
| 89 | * |
| 90 | * The main function, do_dcsw_op requires: |
| 91 | * x0: The operation type (0-2), as defined in arch.h |
| 92 | * x3: The last cache level to operate on |
| 93 | * x9: clidr_el1 |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 94 | * x10: The cache level to begin operation from |
Andrew Thoelke | 6a5b3a4 | 2014-04-25 10:49:30 +0100 | [diff] [blame] | 95 | * and will carry out the operation on each data cache from level 0 |
| 96 | * to the level in x3 in sequence |
| 97 | * |
| 98 | * The dcsw_op macro sets up the x3 and x9 parameters based on |
| 99 | * clidr_el1 cache information before invoking the main function |
| 100 | * --------------------------------------------------------------- |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 101 | */ |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 102 | |
Andrew Thoelke | 6a5b3a4 | 2014-04-25 10:49:30 +0100 | [diff] [blame] | 103 | .macro dcsw_op shift, fw, ls |
| 104 | mrs x9, clidr_el1 |
| 105 | ubfx x3, x9, \shift, \fw |
| 106 | lsl x3, x3, \ls |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 107 | mov x10, xzr |
Andrew Thoelke | 6a5b3a4 | 2014-04-25 10:49:30 +0100 | [diff] [blame] | 108 | b do_dcsw_op |
| 109 | .endm |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 110 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 111 | func do_dcsw_op |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 112 | cbz x3, exit |
Andrew Thoelke | 6a5b3a4 | 2014-04-25 10:49:30 +0100 | [diff] [blame] | 113 | adr x14, dcsw_loop_table // compute inner loop address |
| 114 | add x14, x14, x0, lsl #5 // inner loop is 8x32-bit instructions |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 115 | mov x0, x9 |
Andrew Thoelke | 6a5b3a4 | 2014-04-25 10:49:30 +0100 | [diff] [blame] | 116 | mov w8, #1 |
| 117 | loop1: |
| 118 | add x2, x10, x10, lsr #1 // work out 3x current cache level |
| 119 | lsr x1, x0, x2 // extract cache type bits from clidr |
| 120 | and x1, x1, #7 // mask the bits for current cache only |
| 121 | cmp x1, #2 // see what cache we have at this level |
Douglas Raillard | 9d92e8c | 2017-03-07 16:36:14 +0000 | [diff] [blame] | 122 | b.lo level_done // nothing to do if no cache or icache |
Andrew Thoelke | 6a5b3a4 | 2014-04-25 10:49:30 +0100 | [diff] [blame] | 123 | |
| 124 | msr csselr_el1, x10 // select current cache level in csselr |
| 125 | isb // isb to sych the new cssr&csidr |
| 126 | mrs x1, ccsidr_el1 // read the new ccsidr |
| 127 | and x2, x1, #7 // extract the length of the cache lines |
| 128 | add x2, x2, #4 // add 4 (line length offset) |
| 129 | ubfx x4, x1, #3, #10 // maximum way number |
| 130 | clz w5, w4 // bit position of way size increment |
| 131 | lsl w9, w4, w5 // w9 = aligned max way number |
| 132 | lsl w16, w8, w5 // w16 = way number loop decrement |
| 133 | orr w9, w10, w9 // w9 = combine way and cache number |
| 134 | ubfx w6, w1, #13, #15 // w6 = max set number |
| 135 | lsl w17, w8, w2 // w17 = set number loop decrement |
| 136 | dsb sy // barrier before we start this level |
| 137 | br x14 // jump to DC operation specific loop |
| 138 | |
| 139 | .macro dcsw_loop _op |
| 140 | loop2_\_op: |
| 141 | lsl w7, w6, w2 // w7 = aligned max set number |
| 142 | |
| 143 | loop3_\_op: |
| 144 | orr w11, w9, w7 // combine cache, way and set number |
| 145 | dc \_op, x11 |
| 146 | subs w7, w7, w17 // decrement set number |
Douglas Raillard | 9d92e8c | 2017-03-07 16:36:14 +0000 | [diff] [blame] | 147 | b.hs loop3_\_op |
Andrew Thoelke | 6a5b3a4 | 2014-04-25 10:49:30 +0100 | [diff] [blame] | 148 | |
| 149 | subs x9, x9, x16 // decrement way number |
Douglas Raillard | 9d92e8c | 2017-03-07 16:36:14 +0000 | [diff] [blame] | 150 | b.hs loop2_\_op |
Andrew Thoelke | 6a5b3a4 | 2014-04-25 10:49:30 +0100 | [diff] [blame] | 151 | |
| 152 | b level_done |
| 153 | .endm |
| 154 | |
| 155 | level_done: |
| 156 | add x10, x10, #2 // increment cache number |
| 157 | cmp x3, x10 |
Douglas Raillard | 9d92e8c | 2017-03-07 16:36:14 +0000 | [diff] [blame] | 158 | b.hi loop1 |
Andrew Thoelke | 6a5b3a4 | 2014-04-25 10:49:30 +0100 | [diff] [blame] | 159 | msr csselr_el1, xzr // select cache level 0 in csselr |
| 160 | dsb sy // barrier to complete final cache operation |
| 161 | isb |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 162 | exit: |
| 163 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 164 | endfunc do_dcsw_op |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 165 | |
Andrew Thoelke | 6a5b3a4 | 2014-04-25 10:49:30 +0100 | [diff] [blame] | 166 | dcsw_loop_table: |
| 167 | dcsw_loop isw |
| 168 | dcsw_loop cisw |
| 169 | dcsw_loop csw |
| 170 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 171 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 172 | func dcsw_op_louis |
Andrew Thoelke | 6a5b3a4 | 2014-04-25 10:49:30 +0100 | [diff] [blame] | 173 | dcsw_op #LOUIS_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 174 | endfunc dcsw_op_louis |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 175 | |
| 176 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 177 | func dcsw_op_all |
Andrew Thoelke | 6a5b3a4 | 2014-04-25 10:49:30 +0100 | [diff] [blame] | 178 | dcsw_op #LOC_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 179 | endfunc dcsw_op_all |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 180 | |
| 181 | /* --------------------------------------------------------------- |
| 182 | * Helper macro for data cache operations by set/way for the |
| 183 | * level specified |
| 184 | * --------------------------------------------------------------- |
| 185 | */ |
| 186 | .macro dcsw_op_level level |
| 187 | mrs x9, clidr_el1 |
| 188 | mov x3, \level |
| 189 | sub x10, x3, #2 |
| 190 | b do_dcsw_op |
| 191 | .endm |
| 192 | |
| 193 | /* --------------------------------------------------------------- |
| 194 | * Data cache operations by set/way for level 1 cache |
| 195 | * |
| 196 | * The main function, do_dcsw_op requires: |
| 197 | * x0: The operation type (0-2), as defined in arch.h |
| 198 | * --------------------------------------------------------------- |
| 199 | */ |
| 200 | func dcsw_op_level1 |
| 201 | dcsw_op_level #(1 << LEVEL_SHIFT) |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 202 | endfunc dcsw_op_level1 |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 203 | |
| 204 | /* --------------------------------------------------------------- |
| 205 | * Data cache operations by set/way for level 2 cache |
| 206 | * |
| 207 | * The main function, do_dcsw_op requires: |
| 208 | * x0: The operation type (0-2), as defined in arch.h |
| 209 | * --------------------------------------------------------------- |
| 210 | */ |
| 211 | func dcsw_op_level2 |
| 212 | dcsw_op_level #(2 << LEVEL_SHIFT) |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 213 | endfunc dcsw_op_level2 |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 214 | |
| 215 | /* --------------------------------------------------------------- |
| 216 | * Data cache operations by set/way for level 3 cache |
| 217 | * |
| 218 | * The main function, do_dcsw_op requires: |
| 219 | * x0: The operation type (0-2), as defined in arch.h |
| 220 | * --------------------------------------------------------------- |
| 221 | */ |
| 222 | func dcsw_op_level3 |
| 223 | dcsw_op_level #(3 << LEVEL_SHIFT) |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 224 | endfunc dcsw_op_level3 |