Jiafei Pan | 3202c3b | 2021-01-04 16:03:46 +0800 | [diff] [blame] | 1 | # Copyright 2020-2021 NXP |
| 2 | # |
| 3 | # SPDX-License-Identifier: BSD-3-Clause |
| 4 | # |
| 5 | |
| 6 | # Include build macros, for example: SET_NXP_MAKE_FLAG |
| 7 | include plat/nxp/common/plat_make_helper/plat_build_macros.mk |
| 8 | |
| 9 | # Adding platform specific defines |
| 10 | |
| 11 | $(eval $(call add_define_val,BOARD,'"${BOARD}"')) |
| 12 | |
| 13 | ifeq (${POVDD_ENABLE},yes) |
| 14 | $(eval $(call add_define,CONFIG_POVDD_ENABLE)) |
| 15 | endif |
| 16 | |
| 17 | ifneq (${FLASH_TYPE},) |
| 18 | $(eval $(call add_define,CONFIG_${FLASH_TYPE})) |
| 19 | endif |
| 20 | |
| 21 | ifneq (${XSPI_FLASH_SZ},) |
| 22 | $(eval $(call add_define_val,NXP_FLEXSPI_FLASH_SIZE,${XSPI_FLASH_SZ})) |
| 23 | endif |
| 24 | |
| 25 | ifneq (${QSPI_FLASH_SZ},) |
| 26 | $(eval $(call add_define_val,NXP_QSPI_FLASH_SIZE,${QSPI_FLASH_SZ})) |
| 27 | endif |
| 28 | |
| 29 | ifneq (${NOR_FLASH_SZ},) |
| 30 | $(eval $(call add_define_val,NXP_NOR_FLASH_SIZE,${NOR_FLASH_SZ})) |
| 31 | endif |
| 32 | |
| 33 | |
| 34 | ifneq (${FSPI_ERASE_4K},) |
| 35 | $(eval $(call add_define_val,CONFIG_FSPI_ERASE_4K,${FSPI_ERASE_4K})) |
| 36 | endif |
| 37 | |
| 38 | ifneq (${NUM_OF_DDRC},) |
| 39 | $(eval $(call add_define_val,NUM_OF_DDRC,${NUM_OF_DDRC})) |
| 40 | endif |
| 41 | |
| 42 | ifeq (${CONFIG_DDR_NODIMM},1) |
| 43 | $(eval $(call add_define,CONFIG_DDR_NODIMM)) |
| 44 | DDRC_NUM_DIMM := 1 |
| 45 | endif |
| 46 | |
| 47 | ifneq (${DDRC_NUM_DIMM},) |
| 48 | $(eval $(call add_define_val,DDRC_NUM_DIMM,${DDRC_NUM_DIMM})) |
| 49 | endif |
| 50 | |
| 51 | ifneq (${DDRC_NUM_CS},) |
| 52 | $(eval $(call add_define_val,DDRC_NUM_CS,${DDRC_NUM_CS})) |
| 53 | endif |
| 54 | |
| 55 | ifeq (${DDR_ADDR_DEC},yes) |
| 56 | $(eval $(call add_define,CONFIG_DDR_ADDR_DEC)) |
| 57 | endif |
| 58 | |
| 59 | ifeq (${DDR_ECC_EN},yes) |
| 60 | $(eval $(call add_define,CONFIG_DDR_ECC_EN)) |
| 61 | endif |
| 62 | |
| 63 | ifeq (${CONFIG_STATIC_DDR},1) |
| 64 | $(eval $(call add_define,CONFIG_STATIC_DDR)) |
| 65 | endif |
| 66 | |
| 67 | # Platform can control the base address for non-volatile storage. |
| 68 | #$(eval $(call add_define_val,NV_STORAGE_BASE_ADDR,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - 2 * ${NXP_XSPI_NOR_UNIT_SIZE}')) |
| 69 | |
| 70 | ifeq (${WARM_BOOT},yes) |
| 71 | $(eval $(call add_define_val,PHY_TRAINING_REGS_ON_FLASH,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - ${NXP_XSPI_NOR_UNIT_SIZE}')) |
| 72 | endif |
Jiafei Pan | 85f60bd | 2021-04-27 14:47:52 +0800 | [diff] [blame] | 73 | |
| 74 | # Selecting Boot Source for the TFA images. |
| 75 | define add_boot_mode_define |
| 76 | ifeq ($(1),qspi) |
| 77 | $$(eval $$(call SET_NXP_MAKE_FLAG,QSPI_NEEDED,BL2)) |
| 78 | $$(eval $$(call add_define,QSPI_BOOT)) |
| 79 | else ifeq ($(1),sd) |
| 80 | $$(eval $$(call SET_NXP_MAKE_FLAG,SD_MMC_NEEDED,BL2)) |
| 81 | $$(eval $$(call add_define,SD_BOOT)) |
| 82 | else ifeq ($(1),emmc) |
| 83 | $$(eval $$(call SET_NXP_MAKE_FLAG,SD_MMC_NEEDED,BL2)) |
| 84 | $$(eval $$(call add_define,EMMC_BOOT)) |
| 85 | else ifeq ($(1),nor) |
| 86 | $$(eval $$(call SET_NXP_MAKE_FLAG,IFC_NOR_NEEDED,BL2)) |
| 87 | $$(eval $$(call add_define,NOR_BOOT)) |
| 88 | else ifeq ($(1),nand) |
| 89 | $$(eval $$(call SET_NXP_MAKE_FLAG,IFC_NAND_NEEDED,BL2)) |
| 90 | $$(eval $$(call add_define,NAND_BOOT)) |
| 91 | else ifeq ($(1),flexspi_nor) |
| 92 | $$(eval $$(call SET_NXP_MAKE_FLAG,XSPI_NEEDED,BL2)) |
| 93 | $$(eval $$(call add_define,FLEXSPI_NOR_BOOT)) |
| 94 | else |
| 95 | $$(error $(PLAT) Cannot Support Boot Mode: $(BOOT_MODE)) |
| 96 | endif |
| 97 | endef |
| 98 | |
| 99 | ifneq (,$(findstring $(BOOT_MODE),$(SUPPORTED_BOOT_MODE))) |
| 100 | $(eval $(call add_boot_mode_define,$(strip $(BOOT_MODE)))) |
| 101 | else |
| 102 | $(error $(PLAT) Un-supported Boot Mode = $(BOOT_MODE)) |
| 103 | endif |