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git01.mediatek.com / filogic / atf / c36e97f7ce6273bd16149f01ec0f78ce041d0e3a / . / fdts / stm32mp157c-odyssey-som.dtsi
blob: 6bed33968f730e0e3180f3bad13111636f6ef1f9 [file] [log] [blame]
Grzegorz Szymaszek2366adc2021-04-21 19:46:18 +0200[diff] [blame]1/*
2 * Copyright (C) 2019, STMicroelectronics. All Rights Reserved.
3 * Copyright (C) 2021, Grzegorz Szymaszek.
4 *
5 * SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
6 */
7
8#include "stm32mp157.dtsi"
9#include "stm32mp15xc.dtsi"
10#include "stm32mp15-pinctrl.dtsi"
11#include "stm32mp15xxac-pinctrl.dtsi"
12#include <dt-bindings/clock/stm32mp1-clksrc.h>
13#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
14
15/ {
16 memory@c0000000 {
17 device_type = "memory";
18 reg = <0xc0000000 0x20000000>;
19 };
20
21 vin: vin {
22 compatible = "regulator-fixed";
23 regulator-name = "vin";
24 regulator-min-microvolt = <5000000>;
25 regulator-max-microvolt = <5000000>;
26 regulator-always-on;
27 };
28};
29
30&bsec {
31 board_id: board_id@ec {
32 reg = <0xec 0x4>;
33 st,non-secure-otp;
34 };
35};
36
37&clk_hse {
38 st,digbypass;
39};
40
41&cpu0 {
42 cpu-supply = <&vddcore>;
43};
44
45&cpu1 {
46 cpu-supply = <&vddcore>;
47};
48
49&cryp1 {
50 status = "okay";
51};
52
53&hash1 {
54 status = "okay";
55};
56
57&i2c2 {
58 pinctrl-names = "default";
59 pinctrl-0 = <&i2c2_pins_a>;
60 clock-frequency = <400000>;
61 i2c-scl-rising-time-ns = <185>;
62 i2c-scl-falling-time-ns = <20>;
63 status = "okay";
64
65 pmic: stpmic@33 {
66 compatible = "st,stpmic1";
67 reg = <0x33>;
68 interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
69 interrupt-controller;
70 #interrupt-cells = <2>;
71 status = "okay";
72
73 regulators {
74 compatible = "st,stpmic1-regulators";
75 buck1-supply = <&vin>;
76 buck2-supply = <&vin>;
77 buck3-supply = <&vin>;
78 buck4-supply = <&vin>;
79 ldo1-supply = <&v3v3>;
80 ldo2-supply = <&vin>;
81 ldo3-supply = <&vdd_ddr>;
82 ldo4-supply = <&vin>;
83 ldo5-supply = <&vin>;
84 ldo6-supply = <&v3v3>;
85 vref_ddr-supply = <&vin>;
86 boost-supply = <&vin>;
87 pwr_sw1-supply = <&bst_out>;
88 pwr_sw2-supply = <&bst_out>;
89
90 vddcore: buck1 {
91 regulator-name = "vddcore";
92 regulator-min-microvolt = <1200000>;
93 regulator-max-microvolt = <1350000>;
94 regulator-always-on;
95 regulator-initial-mode = <0>;
96 regulator-over-current-protection;
97 };
98
99 vdd_ddr: buck2 {
100 regulator-name = "vdd_ddr";
101 regulator-min-microvolt = <1350000>;
102 regulator-max-microvolt = <1350000>;
103 regulator-always-on;
104 regulator-initial-mode = <0>;
105 regulator-over-current-protection;
106 };
107
108 vdd: buck3 {
109 regulator-name = "vdd";
110 regulator-min-microvolt = <3300000>;
111 regulator-max-microvolt = <3300000>;
112 regulator-always-on;
113 st,mask-reset;
114 regulator-initial-mode = <0>;
115 regulator-over-current-protection;
116 };
117
118 v3v3: buck4 {
119 regulator-name = "v3v3";
120 regulator-min-microvolt = <3300000>;
121 regulator-max-microvolt = <3300000>;
122 regulator-always-on;
123 regulator-over-current-protection;
124 regulator-initial-mode = <0>;
125 };
126
127 v1v8_audio: ldo1 {
128 regulator-name = "v1v8_audio";
129 regulator-min-microvolt = <1800000>;
130 regulator-max-microvolt = <1800000>;
131 regulator-always-on;
132 };
133
134 v3v3_hdmi: ldo2 {
135 regulator-name = "v3v3_hdmi";
136 regulator-min-microvolt = <3300000>;
137 regulator-max-microvolt = <3300000>;
138 regulator-always-on;
139 };
140
141 vtt_ddr: ldo3 {
142 regulator-name = "vtt_ddr";
143 regulator-min-microvolt = <500000>;
144 regulator-max-microvolt = <750000>;
145 regulator-always-on;
146 regulator-over-current-protection;
147 };
148
149 vdd_usb: ldo4 {
150 regulator-name = "vdd_usb";
151 regulator-min-microvolt = <3300000>;
152 regulator-max-microvolt = <3300000>;
153 regulator-always-on;
154 };
155
156 vdda: ldo5 {
157 regulator-name = "vdda";
158 regulator-min-microvolt = <2900000>;
159 regulator-max-microvolt = <2900000>;
160 regulator-boot-on;
161 };
162
163 v1v2_hdmi: ldo6 {
164 regulator-name = "v1v2_hdmi";
165 regulator-min-microvolt = <1200000>;
166 regulator-max-microvolt = <1200000>;
167 regulator-always-on;
168 };
169
170 vref_ddr: vref_ddr {
171 regulator-name = "vref_ddr";
172 regulator-always-on;
173 regulator-over-current-protection;
174 };
175
176 bst_out: boost {
177 regulator-name = "bst_out";
178 };
179
180 vbus_otg: pwr_sw1 {
181 regulator-name = "vbus_otg";
182 };
183
184 vbus_sw: pwr_sw2 {
185 regulator-name = "vbus_sw";
186 regulator-active-discharge = <1>;
187 };
188 };
189
190 pmic_watchdog: watchdog {
191 compatible = "st,stpmic1-wdt";
192 status = "disabled";
193 };
194 };
195};
196
197&iwdg2 {
198 timeout-sec = <32>;
199 status = "okay";
200};
201
202&pwr_regulators {
203 vdd-supply = <&vdd>;
204 vdd_3v3_usbfs-supply = <&vdd_usb>;
205};
206
207&rcc {
208 secure-status = "disabled";
209 st,clksrc = <
210 CLK_MPU_PLL1P
211 CLK_AXI_PLL2P
212 CLK_MCU_PLL3P
213 CLK_PLL12_HSE
214 CLK_PLL3_HSE
215 CLK_PLL4_HSE
216 CLK_RTC_LSE
217 CLK_MCO1_DISABLED
218 CLK_MCO2_DISABLED
219 >;
220
221 st,clkdiv = <
222 1 /*MPU*/
223 0 /*AXI*/
224 0 /*MCU*/
225 1 /*APB1*/
226 1 /*APB2*/
227 1 /*APB3*/
228 1 /*APB4*/
229 2 /*APB5*/
230 23 /*RTC*/
231 0 /*MCO1*/
232 0 /*MCO2*/
233 >;
234
235 st,pkcs = <
236 CLK_CKPER_HSE
237 CLK_FMC_ACLK
238 CLK_QSPI_ACLK
239 CLK_ETH_PLL4P
240 CLK_SDMMC12_PLL4P
241 CLK_DSI_DSIPLL
242 CLK_STGEN_HSE
243 CLK_USBPHY_HSE
244 CLK_SPI2S1_PLL3Q
245 CLK_SPI2S23_PLL3Q
246 CLK_SPI45_HSI
247 CLK_SPI6_HSI
248 CLK_I2C46_HSI
249 CLK_SDMMC3_PLL4P
250 CLK_USBO_USBPHY
251 CLK_ADC_CKPER
252 CLK_CEC_LSE
253 CLK_I2C12_HSI
254 CLK_I2C35_HSI
255 CLK_UART1_HSI
256 CLK_UART24_HSI
257 CLK_UART35_HSI
258 CLK_UART6_HSI
259 CLK_UART78_HSI
260 CLK_SPDIF_PLL4P
261 CLK_FDCAN_PLL4R
262 CLK_SAI1_PLL3Q
263 CLK_SAI2_PLL3Q
264 CLK_SAI3_PLL3Q
265 CLK_SAI4_PLL3Q
266 CLK_RNG1_LSI
267 CLK_RNG2_LSI
268 CLK_LPTIM1_PCLK1
269 CLK_LPTIM23_PCLK3
270 CLK_LPTIM45_LSE
271 >;
272
273 /* VCO = 1300.0 MHz => P = 650 (CPU) */
274 pll1: st,pll@0 {
275 compatible = "st,stm32mp1-pll";
276 reg = <0>;
277 cfg = <2 80 0 0 0 PQR(1,0,0)>;
278 frac = <0x800>;
279 };
280
281 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
282 pll2: st,pll@1 {
283 compatible = "st,stm32mp1-pll";
284 reg = <1>;
285 cfg = <2 65 1 0 0 PQR(1,1,1)>;
286 frac = <0x1400>;
287 };
288
289 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
290 pll3: st,pll@2 {
291 compatible = "st,stm32mp1-pll";
292 reg = <2>;
293 cfg = <1 33 1 16 36 PQR(1,1,1)>;
294 frac = <0x1a04>;
295 };
296
297 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
298 pll4: st,pll@3 {
299 compatible = "st,stm32mp1-pll";
300 reg = <3>;
301 cfg = <3 98 5 7 7 PQR(1,1,1)>;
302 };
303};
304
305&rng1 {
306 status = "okay";
307};
308
309&rtc {
310 status = "okay";
311};
312
313&sdmmc2 {
314 pinctrl-names = "default";
315 pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_d>;
316 non-removable;
317 no-sd;
318 no-sdio;
319 st,neg-edge;
320 bus-width = <8>;
321 vmmc-supply = <&v3v3>;
322 vqmmc-supply = <&vdd>;
323 mmc-ddr-3_3v;
324 status = "okay";
325};