Dan Handley | e2c27f5 | 2014-08-01 17:58:27 +0100 | [diff] [blame] | 1 | /* |
Achin Gupta | 6b4ec24 | 2021-10-04 20:13:36 +0100 | [diff] [blame] | 2 | * Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved. |
Dan Handley | e2c27f5 | 2014-08-01 17:58:27 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Dan Handley | e2c27f5 | 2014-08-01 17:58:27 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 7 | #ifndef TSP_PRIVATE_H |
| 8 | #define TSP_PRIVATE_H |
Dan Handley | e2c27f5 | 2014-08-01 17:58:27 +0100 | [diff] [blame] | 9 | |
Achin Gupta | 6b4ec24 | 2021-10-04 20:13:36 +0100 | [diff] [blame] | 10 | /******************************************************************************* |
| 11 | * The TSP memory footprint starts at address BL32_BASE and ends with the |
| 12 | * linker symbol __BL32_END__. Use these addresses to compute the TSP image |
| 13 | * size. |
| 14 | ******************************************************************************/ |
| 15 | #define BL32_TOTAL_LIMIT BL32_END |
| 16 | #define BL32_TOTAL_SIZE (BL32_TOTAL_LIMIT - (unsigned long) BL32_BASE) |
Dan Handley | e2c27f5 | 2014-08-01 17:58:27 +0100 | [diff] [blame] | 17 | |
Julius Werner | 53456fc | 2019-07-09 13:49:11 -0700 | [diff] [blame] | 18 | #ifndef __ASSEMBLER__ |
Dan Handley | e2c27f5 | 2014-08-01 17:58:27 +0100 | [diff] [blame] | 19 | |
Dan Handley | e2c27f5 | 2014-08-01 17:58:27 +0100 | [diff] [blame] | 20 | #include <stdint.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 21 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 22 | #include <bl32/tsp/tsp.h> |
| 23 | #include <lib/cassert.h> |
| 24 | #include <lib/spinlock.h> |
Achin Gupta | 6b4ec24 | 2021-10-04 20:13:36 +0100 | [diff] [blame] | 25 | #include <smccc_helpers.h> |
Dan Handley | e2c27f5 | 2014-08-01 17:58:27 +0100 | [diff] [blame] | 26 | |
| 27 | typedef struct work_statistics { |
Soby Mathew | bec9851 | 2015-09-03 18:29:38 +0100 | [diff] [blame] | 28 | /* Number of s-el1 interrupts on this cpu */ |
| 29 | uint32_t sel1_intr_count; |
Soby Mathew | bc91282 | 2015-09-22 12:01:18 +0100 | [diff] [blame] | 30 | /* Number of non s-el1 interrupts on this cpu which preempted TSP */ |
| 31 | uint32_t preempt_intr_count; |
Soby Mathew | bec9851 | 2015-09-03 18:29:38 +0100 | [diff] [blame] | 32 | /* Number of sync s-el1 interrupts on this cpu */ |
| 33 | uint32_t sync_sel1_intr_count; |
| 34 | /* Number of s-el1 interrupts returns on this cpu */ |
| 35 | uint32_t sync_sel1_intr_ret_count; |
Dan Handley | e2c27f5 | 2014-08-01 17:58:27 +0100 | [diff] [blame] | 36 | uint32_t smc_count; /* Number of returns on this cpu */ |
| 37 | uint32_t eret_count; /* Number of entries on this cpu */ |
| 38 | uint32_t cpu_on_count; /* Number of cpu on requests */ |
| 39 | uint32_t cpu_off_count; /* Number of cpu off requests */ |
| 40 | uint32_t cpu_suspend_count; /* Number of cpu suspend requests */ |
| 41 | uint32_t cpu_resume_count; /* Number of cpu resume requests */ |
| 42 | } __aligned(CACHE_WRITEBACK_GRANULE) work_statistics_t; |
| 43 | |
Dan Handley | e2c27f5 | 2014-08-01 17:58:27 +0100 | [diff] [blame] | 44 | /* Macros to access members of the above structure using their offsets */ |
| 45 | #define read_sp_arg(args, offset) ((args)->_regs[offset >> 3]) |
| 46 | #define write_sp_arg(args, offset, val) (((args)->_regs[offset >> 3]) \ |
| 47 | = val) |
Dan Handley | e2c27f5 | 2014-08-01 17:58:27 +0100 | [diff] [blame] | 48 | |
Alexei Fedorov | 7d616ee | 2020-11-13 12:36:49 +0000 | [diff] [blame] | 49 | uint128_t tsp_get_magic(void); |
Dan Handley | e2c27f5 | 2014-08-01 17:58:27 +0100 | [diff] [blame] | 50 | |
Achin Gupta | 6b4ec24 | 2021-10-04 20:13:36 +0100 | [diff] [blame] | 51 | smc_args_t *set_smc_args(uint64_t arg0, |
| 52 | uint64_t arg1, |
| 53 | uint64_t arg2, |
| 54 | uint64_t arg3, |
| 55 | uint64_t arg4, |
| 56 | uint64_t arg5, |
| 57 | uint64_t arg6, |
| 58 | uint64_t arg7); |
| 59 | smc_args_t *tsp_cpu_resume_main(uint64_t max_off_pwrlvl, |
Dan Handley | e2c27f5 | 2014-08-01 17:58:27 +0100 | [diff] [blame] | 60 | uint64_t arg1, |
| 61 | uint64_t arg2, |
| 62 | uint64_t arg3, |
| 63 | uint64_t arg4, |
| 64 | uint64_t arg5, |
| 65 | uint64_t arg6, |
| 66 | uint64_t arg7); |
Achin Gupta | 6b4ec24 | 2021-10-04 20:13:36 +0100 | [diff] [blame] | 67 | smc_args_t *tsp_cpu_suspend_main(uint64_t arg0, |
Dan Handley | e2c27f5 | 2014-08-01 17:58:27 +0100 | [diff] [blame] | 68 | uint64_t arg1, |
| 69 | uint64_t arg2, |
| 70 | uint64_t arg3, |
| 71 | uint64_t arg4, |
| 72 | uint64_t arg5, |
| 73 | uint64_t arg6, |
| 74 | uint64_t arg7); |
Achin Gupta | 6b4ec24 | 2021-10-04 20:13:36 +0100 | [diff] [blame] | 75 | smc_args_t *tsp_cpu_on_main(void); |
| 76 | smc_args_t *tsp_cpu_off_main(uint64_t arg0, |
Dan Handley | e2c27f5 | 2014-08-01 17:58:27 +0100 | [diff] [blame] | 77 | uint64_t arg1, |
| 78 | uint64_t arg2, |
| 79 | uint64_t arg3, |
| 80 | uint64_t arg4, |
| 81 | uint64_t arg5, |
| 82 | uint64_t arg6, |
| 83 | uint64_t arg7); |
| 84 | |
| 85 | /* Generic Timer functions */ |
| 86 | void tsp_generic_timer_start(void); |
| 87 | void tsp_generic_timer_handler(void); |
| 88 | void tsp_generic_timer_stop(void); |
| 89 | void tsp_generic_timer_save(void); |
| 90 | void tsp_generic_timer_restore(void); |
| 91 | |
Soby Mathew | bec9851 | 2015-09-03 18:29:38 +0100 | [diff] [blame] | 92 | /* S-EL1 interrupt management functions */ |
| 93 | void tsp_update_sync_sel1_intr_stats(uint32_t type, uint64_t elr_el3); |
Dan Handley | e2c27f5 | 2014-08-01 17:58:27 +0100 | [diff] [blame] | 94 | |
| 95 | |
| 96 | /* Data structure to keep track of TSP statistics */ |
| 97 | extern spinlock_t console_lock; |
| 98 | extern work_statistics_t tsp_stats[PLATFORM_CORE_COUNT]; |
| 99 | |
| 100 | /* Vector table of jumps */ |
| 101 | extern tsp_vectors_t tsp_vector_table; |
| 102 | |
Roberto Vargas | d4b35e1 | 2018-02-12 12:36:17 +0000 | [diff] [blame] | 103 | /* functions */ |
| 104 | int32_t tsp_common_int_handler(void); |
| 105 | int32_t tsp_handle_preemption(void); |
| 106 | |
Achin Gupta | 6b4ec24 | 2021-10-04 20:13:36 +0100 | [diff] [blame] | 107 | smc_args_t *tsp_abort_smc_handler(uint64_t func, |
Roberto Vargas | d4b35e1 | 2018-02-12 12:36:17 +0000 | [diff] [blame] | 108 | uint64_t arg1, |
| 109 | uint64_t arg2, |
| 110 | uint64_t arg3, |
| 111 | uint64_t arg4, |
| 112 | uint64_t arg5, |
| 113 | uint64_t arg6, |
| 114 | uint64_t arg7); |
| 115 | |
Achin Gupta | 6b4ec24 | 2021-10-04 20:13:36 +0100 | [diff] [blame] | 116 | smc_args_t *tsp_smc_handler(uint64_t func, |
| 117 | uint64_t arg1, |
| 118 | uint64_t arg2, |
| 119 | uint64_t arg3, |
| 120 | uint64_t arg4, |
| 121 | uint64_t arg5, |
| 122 | uint64_t arg6, |
| 123 | uint64_t arg7); |
Roberto Vargas | d4b35e1 | 2018-02-12 12:36:17 +0000 | [diff] [blame] | 124 | |
Achin Gupta | 6b4ec24 | 2021-10-04 20:13:36 +0100 | [diff] [blame] | 125 | smc_args_t *tsp_system_reset_main(uint64_t arg0, |
| 126 | uint64_t arg1, |
| 127 | uint64_t arg2, |
| 128 | uint64_t arg3, |
| 129 | uint64_t arg4, |
| 130 | uint64_t arg5, |
| 131 | uint64_t arg6, |
| 132 | uint64_t arg7); |
Roberto Vargas | d4b35e1 | 2018-02-12 12:36:17 +0000 | [diff] [blame] | 133 | |
Achin Gupta | 6b4ec24 | 2021-10-04 20:13:36 +0100 | [diff] [blame] | 134 | smc_args_t *tsp_system_off_main(uint64_t arg0, |
Roberto Vargas | d4b35e1 | 2018-02-12 12:36:17 +0000 | [diff] [blame] | 135 | uint64_t arg1, |
| 136 | uint64_t arg2, |
| 137 | uint64_t arg3, |
| 138 | uint64_t arg4, |
| 139 | uint64_t arg5, |
| 140 | uint64_t arg6, |
| 141 | uint64_t arg7); |
Dan Handley | e2c27f5 | 2014-08-01 17:58:27 +0100 | [diff] [blame] | 142 | |
Roberto Vargas | d4b35e1 | 2018-02-12 12:36:17 +0000 | [diff] [blame] | 143 | uint64_t tsp_main(void); |
Julius Werner | 53456fc | 2019-07-09 13:49:11 -0700 | [diff] [blame] | 144 | #endif /* __ASSEMBLER__ */ |
Dan Handley | e2c27f5 | 2014-08-01 17:58:27 +0100 | [diff] [blame] | 145 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 146 | #endif /* TSP_PRIVATE_H */ |