Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Dan Handley | ab2d31e | 2013-12-02 19:25:12 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <stdio.h> |
| 32 | #include <string.h> |
| 33 | #include <assert.h> |
| 34 | #include <arch_helpers.h> |
| 35 | #include <console.h> |
| 36 | #include <platform.h> |
| 37 | #include <bl_common.h> |
| 38 | #include <bl31.h> |
| 39 | #include <bakery_lock.h> |
| 40 | #include <cci400.h> |
| 41 | #include <gic.h> |
| 42 | #include <fvp_pwrc.h> |
| 43 | /* Only included for error codes */ |
| 44 | #include <psci.h> |
| 45 | |
| 46 | /******************************************************************************* |
| 47 | * FVP handler called when an affinity instance is about to be turned on. The |
| 48 | * level and mpidr determine the affinity instance. |
| 49 | ******************************************************************************/ |
| 50 | int fvp_affinst_on(unsigned long mpidr, |
| 51 | unsigned long sec_entrypoint, |
| 52 | unsigned long ns_entrypoint, |
| 53 | unsigned int afflvl, |
| 54 | unsigned int state) |
| 55 | { |
| 56 | int rc = PSCI_E_SUCCESS; |
| 57 | unsigned long linear_id; |
| 58 | mailbox *fvp_mboxes; |
| 59 | unsigned int psysr; |
| 60 | |
| 61 | if (ns_entrypoint < DRAM_BASE) { |
| 62 | rc = PSCI_E_INVALID_PARAMS; |
| 63 | goto exit; |
| 64 | } |
| 65 | |
| 66 | /* |
| 67 | * It's possible to turn on only affinity level 0 i.e. a cpu |
| 68 | * on the FVP. Ignore any other affinity level. |
| 69 | */ |
| 70 | if (afflvl != MPIDR_AFFLVL0) |
| 71 | goto exit; |
| 72 | |
| 73 | /* |
| 74 | * Ensure that we do not cancel an inflight power off request |
| 75 | * for the target cpu. That would leave it in a zombie wfi. |
| 76 | * Wait for it to power off, program the jump address for the |
| 77 | * target cpu and then program the power controller to turn |
| 78 | * that cpu on |
| 79 | */ |
| 80 | do { |
| 81 | psysr = fvp_pwrc_read_psysr(mpidr); |
| 82 | } while (psysr & PSYSR_AFF_L0); |
| 83 | |
| 84 | linear_id = platform_get_core_pos(mpidr); |
| 85 | fvp_mboxes = (mailbox *) (TZDRAM_BASE + MBOX_OFF); |
| 86 | fvp_mboxes[linear_id].value = sec_entrypoint; |
| 87 | flush_dcache_range((unsigned long) &fvp_mboxes[linear_id], |
| 88 | sizeof(unsigned long)); |
| 89 | |
| 90 | fvp_pwrc_write_pponr(mpidr); |
| 91 | |
| 92 | exit: |
| 93 | return rc; |
| 94 | } |
| 95 | |
| 96 | /******************************************************************************* |
| 97 | * FVP handler called when an affinity instance is about to be turned off. The |
| 98 | * level and mpidr determine the affinity instance. The 'state' arg. allows the |
| 99 | * platform to decide whether the cluster is being turned off and take apt |
| 100 | * actions. |
| 101 | * |
| 102 | * CAUTION: This function is called with coherent stacks so that caches can be |
| 103 | * turned off, flushed and coherency disabled. There is no guarantee that caches |
| 104 | * will remain turned on across calls to this function as each affinity level is |
| 105 | * dealt with. So do not write & read global variables across calls. It will be |
| 106 | * wise to do flush a write to the global to prevent unpredictable results. |
| 107 | ******************************************************************************/ |
| 108 | int fvp_affinst_off(unsigned long mpidr, |
| 109 | unsigned int afflvl, |
| 110 | unsigned int state) |
| 111 | { |
| 112 | int rc = PSCI_E_SUCCESS; |
| 113 | unsigned int gicc_base, ectlr; |
Harry Liebel | 30affd5 | 2013-10-30 17:41:48 +0000 | [diff] [blame] | 114 | unsigned long cpu_setup, cci_setup; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 115 | |
| 116 | switch (afflvl) { |
| 117 | case MPIDR_AFFLVL1: |
| 118 | if (state == PSCI_STATE_OFF) { |
| 119 | /* |
| 120 | * Disable coherency if this cluster is to be |
| 121 | * turned off |
| 122 | */ |
Harry Liebel | 30affd5 | 2013-10-30 17:41:48 +0000 | [diff] [blame] | 123 | cci_setup = platform_get_cfgvar(CONFIG_HAS_CCI); |
| 124 | if (cci_setup) { |
| 125 | cci_disable_coherency(mpidr); |
| 126 | } |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 127 | |
| 128 | /* |
| 129 | * Program the power controller to turn the |
| 130 | * cluster off |
| 131 | */ |
| 132 | fvp_pwrc_write_pcoffr(mpidr); |
| 133 | |
| 134 | } |
| 135 | break; |
| 136 | |
| 137 | case MPIDR_AFFLVL0: |
| 138 | if (state == PSCI_STATE_OFF) { |
| 139 | |
| 140 | /* |
| 141 | * Take this cpu out of intra-cluster coherency if |
| 142 | * the FVP flavour supports the SMP bit. |
| 143 | */ |
| 144 | cpu_setup = platform_get_cfgvar(CONFIG_CPU_SETUP); |
| 145 | if (cpu_setup) { |
| 146 | ectlr = read_cpuectlr(); |
| 147 | ectlr &= ~CPUECTLR_SMP_BIT; |
| 148 | write_cpuectlr(ectlr); |
| 149 | } |
| 150 | |
| 151 | /* |
| 152 | * Prevent interrupts from spuriously waking up |
| 153 | * this cpu |
| 154 | */ |
| 155 | gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR); |
| 156 | gic_cpuif_deactivate(gicc_base); |
| 157 | |
| 158 | /* |
| 159 | * Program the power controller to power this |
| 160 | * cpu off |
| 161 | */ |
| 162 | fvp_pwrc_write_ppoffr(mpidr); |
| 163 | } |
| 164 | break; |
| 165 | |
| 166 | default: |
| 167 | assert(0); |
| 168 | } |
| 169 | |
| 170 | return rc; |
| 171 | } |
| 172 | |
| 173 | /******************************************************************************* |
| 174 | * FVP handler called when an affinity instance is about to be suspended. The |
| 175 | * level and mpidr determine the affinity instance. The 'state' arg. allows the |
| 176 | * platform to decide whether the cluster is being turned off and take apt |
| 177 | * actions. |
| 178 | * |
| 179 | * CAUTION: This function is called with coherent stacks so that caches can be |
| 180 | * turned off, flushed and coherency disabled. There is no guarantee that caches |
| 181 | * will remain turned on across calls to this function as each affinity level is |
| 182 | * dealt with. So do not write & read global variables across calls. It will be |
| 183 | * wise to do flush a write to the global to prevent unpredictable results. |
| 184 | ******************************************************************************/ |
| 185 | int fvp_affinst_suspend(unsigned long mpidr, |
| 186 | unsigned long sec_entrypoint, |
| 187 | unsigned long ns_entrypoint, |
| 188 | unsigned int afflvl, |
| 189 | unsigned int state) |
| 190 | { |
| 191 | int rc = PSCI_E_SUCCESS; |
| 192 | unsigned int gicc_base, ectlr; |
Harry Liebel | 30affd5 | 2013-10-30 17:41:48 +0000 | [diff] [blame] | 193 | unsigned long cpu_setup, cci_setup, linear_id; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 194 | mailbox *fvp_mboxes; |
| 195 | |
| 196 | /* Cannot allow NS world to execute trusted firmware code */ |
| 197 | if (ns_entrypoint < DRAM_BASE) { |
| 198 | rc = PSCI_E_INVALID_PARAMS; |
| 199 | goto exit; |
| 200 | } |
| 201 | |
| 202 | switch (afflvl) { |
| 203 | case MPIDR_AFFLVL1: |
| 204 | if (state == PSCI_STATE_OFF) { |
| 205 | /* |
| 206 | * Disable coherency if this cluster is to be |
| 207 | * turned off |
| 208 | */ |
Harry Liebel | 30affd5 | 2013-10-30 17:41:48 +0000 | [diff] [blame] | 209 | cci_setup = platform_get_cfgvar(CONFIG_HAS_CCI); |
| 210 | if (cci_setup) { |
| 211 | cci_disable_coherency(mpidr); |
| 212 | } |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 213 | |
| 214 | /* |
| 215 | * Program the power controller to turn the |
| 216 | * cluster off |
| 217 | */ |
| 218 | fvp_pwrc_write_pcoffr(mpidr); |
| 219 | |
| 220 | } |
| 221 | break; |
| 222 | |
| 223 | case MPIDR_AFFLVL0: |
| 224 | if (state == PSCI_STATE_OFF) { |
| 225 | /* |
| 226 | * Take this cpu out of intra-cluster coherency if |
| 227 | * the FVP flavour supports the SMP bit. |
| 228 | */ |
| 229 | cpu_setup = platform_get_cfgvar(CONFIG_CPU_SETUP); |
| 230 | if (cpu_setup) { |
| 231 | ectlr = read_cpuectlr(); |
| 232 | ectlr &= ~CPUECTLR_SMP_BIT; |
| 233 | write_cpuectlr(ectlr); |
| 234 | } |
| 235 | |
| 236 | /* Program the jump address for the target cpu */ |
| 237 | linear_id = platform_get_core_pos(mpidr); |
| 238 | fvp_mboxes = (mailbox *) (TZDRAM_BASE + MBOX_OFF); |
| 239 | fvp_mboxes[linear_id].value = sec_entrypoint; |
| 240 | flush_dcache_range((unsigned long) &fvp_mboxes[linear_id], |
| 241 | sizeof(unsigned long)); |
| 242 | |
| 243 | /* |
| 244 | * Prevent interrupts from spuriously waking up |
| 245 | * this cpu |
| 246 | */ |
| 247 | gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR); |
| 248 | gic_cpuif_deactivate(gicc_base); |
| 249 | |
| 250 | /* |
| 251 | * Program the power controller to power this |
| 252 | * cpu off and enable wakeup interrupts. |
| 253 | */ |
Achin Gupta | b127cdb | 2013-11-12 16:40:00 +0000 | [diff] [blame] | 254 | fvp_pwrc_set_wen(mpidr); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 255 | fvp_pwrc_write_ppoffr(mpidr); |
| 256 | } |
| 257 | break; |
| 258 | |
| 259 | default: |
| 260 | assert(0); |
| 261 | } |
| 262 | |
| 263 | exit: |
| 264 | return rc; |
| 265 | } |
| 266 | |
| 267 | /******************************************************************************* |
| 268 | * FVP handler called when an affinity instance has just been powered on after |
| 269 | * being turned off earlier. The level and mpidr determine the affinity |
| 270 | * instance. The 'state' arg. allows the platform to decide whether the cluster |
| 271 | * was turned off prior to wakeup and do what's necessary to setup it up |
| 272 | * correctly. |
| 273 | ******************************************************************************/ |
| 274 | int fvp_affinst_on_finish(unsigned long mpidr, |
| 275 | unsigned int afflvl, |
| 276 | unsigned int state) |
| 277 | { |
| 278 | int rc = PSCI_E_SUCCESS; |
Harry Liebel | 30affd5 | 2013-10-30 17:41:48 +0000 | [diff] [blame] | 279 | unsigned long linear_id, cpu_setup, cci_setup; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 280 | mailbox *fvp_mboxes; |
| 281 | unsigned int gicd_base, gicc_base, reg_val, ectlr; |
| 282 | |
| 283 | switch (afflvl) { |
| 284 | |
| 285 | case MPIDR_AFFLVL1: |
| 286 | /* Enable coherency if this cluster was off */ |
Harry Liebel | 30affd5 | 2013-10-30 17:41:48 +0000 | [diff] [blame] | 287 | if (state == PSCI_STATE_OFF) { |
| 288 | cci_setup = platform_get_cfgvar(CONFIG_HAS_CCI); |
| 289 | if (cci_setup) { |
| 290 | cci_enable_coherency(mpidr); |
| 291 | } |
| 292 | } |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 293 | break; |
| 294 | |
| 295 | case MPIDR_AFFLVL0: |
| 296 | /* |
| 297 | * Ignore the state passed for a cpu. It could only have |
| 298 | * been off if we are here. |
| 299 | */ |
| 300 | |
| 301 | /* |
| 302 | * Turn on intra-cluster coherency if the FVP flavour supports |
| 303 | * it. |
| 304 | */ |
| 305 | cpu_setup = platform_get_cfgvar(CONFIG_CPU_SETUP); |
| 306 | if (cpu_setup) { |
| 307 | ectlr = read_cpuectlr(); |
| 308 | ectlr |= CPUECTLR_SMP_BIT; |
| 309 | write_cpuectlr(ectlr); |
| 310 | } |
| 311 | |
Achin Gupta | b127cdb | 2013-11-12 16:40:00 +0000 | [diff] [blame] | 312 | /* |
| 313 | * Clear PWKUPR.WEN bit to ensure interrupts do not interfere |
| 314 | * with a cpu power down unless the bit is set again |
| 315 | */ |
| 316 | fvp_pwrc_clr_wen(mpidr); |
| 317 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 318 | /* Zero the jump address in the mailbox for this cpu */ |
| 319 | fvp_mboxes = (mailbox *) (TZDRAM_BASE + MBOX_OFF); |
| 320 | linear_id = platform_get_core_pos(mpidr); |
| 321 | fvp_mboxes[linear_id].value = 0; |
| 322 | flush_dcache_range((unsigned long) &fvp_mboxes[linear_id], |
| 323 | sizeof(unsigned long)); |
| 324 | |
| 325 | gicd_base = platform_get_cfgvar(CONFIG_GICD_ADDR); |
| 326 | gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR); |
| 327 | |
| 328 | /* Enable the gic cpu interface */ |
| 329 | gic_cpuif_setup(gicc_base); |
| 330 | |
| 331 | /* TODO: This setup is needed only after a cold boot */ |
| 332 | gic_pcpu_distif_setup(gicd_base); |
| 333 | |
| 334 | /* Allow access to the System counter timer module */ |
| 335 | reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); |
| 336 | reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); |
| 337 | reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT); |
| 338 | mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(0), reg_val); |
| 339 | mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(1), reg_val); |
| 340 | |
| 341 | reg_val = (1 << CNTNSAR_NS_SHIFT(0)) | |
| 342 | (1 << CNTNSAR_NS_SHIFT(1)); |
| 343 | mmio_write_32(SYS_TIMCTL_BASE + CNTNSAR, reg_val); |
| 344 | |
| 345 | break; |
| 346 | |
| 347 | default: |
| 348 | assert(0); |
| 349 | } |
| 350 | |
| 351 | return rc; |
| 352 | } |
| 353 | |
| 354 | /******************************************************************************* |
| 355 | * FVP handler called when an affinity instance has just been powered on after |
| 356 | * having been suspended earlier. The level and mpidr determine the affinity |
| 357 | * instance. |
| 358 | * TODO: At the moment we reuse the on finisher and reinitialize the secure |
| 359 | * context. Need to implement a separate suspend finisher. |
| 360 | ******************************************************************************/ |
| 361 | int fvp_affinst_suspend_finish(unsigned long mpidr, |
| 362 | unsigned int afflvl, |
| 363 | unsigned int state) |
| 364 | { |
| 365 | return fvp_affinst_on_finish(mpidr, afflvl, state); |
| 366 | } |
| 367 | |
| 368 | |
| 369 | /******************************************************************************* |
| 370 | * Export the platform handlers to enable psci to invoke them |
| 371 | ******************************************************************************/ |
| 372 | static plat_pm_ops fvp_plat_pm_ops = { |
| 373 | 0, |
| 374 | fvp_affinst_on, |
| 375 | fvp_affinst_off, |
| 376 | fvp_affinst_suspend, |
| 377 | fvp_affinst_on_finish, |
| 378 | fvp_affinst_suspend_finish, |
| 379 | }; |
| 380 | |
| 381 | /******************************************************************************* |
| 382 | * Export the platform specific power ops & initialize the fvp power controller |
| 383 | ******************************************************************************/ |
| 384 | int platform_setup_pm(plat_pm_ops **plat_ops) |
| 385 | { |
| 386 | *plat_ops = &fvp_plat_pm_ops; |
| 387 | return 0; |
| 388 | } |