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git01.mediatek.com / filogic / atf / c294d82d6f6256e303ac580aa6f69588dc5f7791 / . / plat / nvidia / tegra / soc / t194 / plat_memctrl.c
blob: d5f72b614d39ef43dcf9866535ddfeb0975f4ccf [file] [log] [blame]
Varun Wadekar00759902017-05-31 11:41:00 -0700[diff] [blame]1/*
Pritesh Raithatha45ea6892017-12-18 23:00:05 -0800[diff] [blame]2 * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
Varun Wadekar00759902017-05-31 11:41:00 -0700[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Varun Wadekar128f46a2019-10-24 16:06:12 -0700[diff] [blame]7#include <assert.h>
8#include <common/bl_common.h>
9#include <mce.h>
Varun Wadekar00759902017-05-31 11:41:00 -0700[diff] [blame]10#include <memctrl_v2.h>
Varun Wadekar128f46a2019-10-24 16:06:12 -0700[diff] [blame]11#include <tegra_mc_def.h>
12#include <tegra_platform.h>
Varun Wadekar00759902017-05-31 11:41:00 -0700[diff] [blame]13
14/*******************************************************************************
15 * Array to hold stream_id override config register offsets
16 ******************************************************************************/
17const static uint32_t tegra194_streamid_override_regs[] = {
18 MC_STREAMID_OVERRIDE_CFG_HDAR,
19 MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR,
20 MC_STREAMID_OVERRIDE_CFG_NVENCSRD,
21 MC_STREAMID_OVERRIDE_CFG_SATAR,
22 MC_STREAMID_OVERRIDE_CFG_NVENCSWR,
23 MC_STREAMID_OVERRIDE_CFG_HDAW,
24 MC_STREAMID_OVERRIDE_CFG_SATAW,
25 MC_STREAMID_OVERRIDE_CFG_ISPRA,
26 MC_STREAMID_OVERRIDE_CFG_ISPFALR,
27 MC_STREAMID_OVERRIDE_CFG_ISPWA,
28 MC_STREAMID_OVERRIDE_CFG_ISPWB,
29 MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR,
30 MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW,
31 MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR,
32 MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW,
33 MC_STREAMID_OVERRIDE_CFG_TSECSRD,
34 MC_STREAMID_OVERRIDE_CFG_TSECSWR,
35 MC_STREAMID_OVERRIDE_CFG_SDMMCRA,
36 MC_STREAMID_OVERRIDE_CFG_SDMMCR,
37 MC_STREAMID_OVERRIDE_CFG_SDMMCRAB,
38 MC_STREAMID_OVERRIDE_CFG_SDMMCWA,
39 MC_STREAMID_OVERRIDE_CFG_SDMMCW,
40 MC_STREAMID_OVERRIDE_CFG_SDMMCWAB,
41 MC_STREAMID_OVERRIDE_CFG_VICSRD,
42 MC_STREAMID_OVERRIDE_CFG_VICSWR,
43 MC_STREAMID_OVERRIDE_CFG_VIW,
44 MC_STREAMID_OVERRIDE_CFG_NVDECSRD,
45 MC_STREAMID_OVERRIDE_CFG_NVDECSWR,
46 MC_STREAMID_OVERRIDE_CFG_APER,
47 MC_STREAMID_OVERRIDE_CFG_APEW,
48 MC_STREAMID_OVERRIDE_CFG_NVJPGSRD,
49 MC_STREAMID_OVERRIDE_CFG_NVJPGSWR,
50 MC_STREAMID_OVERRIDE_CFG_SESRD,
51 MC_STREAMID_OVERRIDE_CFG_SESWR,
52 MC_STREAMID_OVERRIDE_CFG_AXIAPR,
53 MC_STREAMID_OVERRIDE_CFG_AXIAPW,
54 MC_STREAMID_OVERRIDE_CFG_ETRR,
55 MC_STREAMID_OVERRIDE_CFG_ETRW,
56 MC_STREAMID_OVERRIDE_CFG_TSECSRDB,
57 MC_STREAMID_OVERRIDE_CFG_TSECSWRB,
58 MC_STREAMID_OVERRIDE_CFG_AXISR,
59 MC_STREAMID_OVERRIDE_CFG_AXISW,
60 MC_STREAMID_OVERRIDE_CFG_EQOSR,
61 MC_STREAMID_OVERRIDE_CFG_EQOSW,
62 MC_STREAMID_OVERRIDE_CFG_UFSHCR,
63 MC_STREAMID_OVERRIDE_CFG_UFSHCW,
64 MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR,
65 MC_STREAMID_OVERRIDE_CFG_BPMPR,
66 MC_STREAMID_OVERRIDE_CFG_BPMPW,
67 MC_STREAMID_OVERRIDE_CFG_BPMPDMAR,
68 MC_STREAMID_OVERRIDE_CFG_BPMPDMAW,
69 MC_STREAMID_OVERRIDE_CFG_AONR,
70 MC_STREAMID_OVERRIDE_CFG_AONW,
71 MC_STREAMID_OVERRIDE_CFG_AONDMAR,
72 MC_STREAMID_OVERRIDE_CFG_AONDMAW,
73 MC_STREAMID_OVERRIDE_CFG_SCER,
74 MC_STREAMID_OVERRIDE_CFG_SCEW,
75 MC_STREAMID_OVERRIDE_CFG_SCEDMAR,
76 MC_STREAMID_OVERRIDE_CFG_SCEDMAW,
77 MC_STREAMID_OVERRIDE_CFG_APEDMAR,
78 MC_STREAMID_OVERRIDE_CFG_APEDMAW,
79 MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1,
80 MC_STREAMID_OVERRIDE_CFG_VICSRD1,
81 MC_STREAMID_OVERRIDE_CFG_NVDECSRD1,
82 MC_STREAMID_OVERRIDE_CFG_VIFALR,
83 MC_STREAMID_OVERRIDE_CFG_VIFALW,
84 MC_STREAMID_OVERRIDE_CFG_DLA0RDA,
85 MC_STREAMID_OVERRIDE_CFG_DLA0FALRDB,
86 MC_STREAMID_OVERRIDE_CFG_DLA0WRA,
87 MC_STREAMID_OVERRIDE_CFG_DLA0FALWRB,
88 MC_STREAMID_OVERRIDE_CFG_DLA1RDA,
89 MC_STREAMID_OVERRIDE_CFG_DLA1FALRDB,
90 MC_STREAMID_OVERRIDE_CFG_DLA1WRA,
91 MC_STREAMID_OVERRIDE_CFG_DLA1FALWRB,
92 MC_STREAMID_OVERRIDE_CFG_PVA0RDA,
93 MC_STREAMID_OVERRIDE_CFG_PVA0RDB,
94 MC_STREAMID_OVERRIDE_CFG_PVA0RDC,
95 MC_STREAMID_OVERRIDE_CFG_PVA0WRA,
96 MC_STREAMID_OVERRIDE_CFG_PVA0WRB,
97 MC_STREAMID_OVERRIDE_CFG_PVA0WRC,
98 MC_STREAMID_OVERRIDE_CFG_PVA1RDA,
99 MC_STREAMID_OVERRIDE_CFG_PVA1RDB,
100 MC_STREAMID_OVERRIDE_CFG_PVA1RDC,
101 MC_STREAMID_OVERRIDE_CFG_PVA1WRA,
102 MC_STREAMID_OVERRIDE_CFG_PVA1WRB,
103 MC_STREAMID_OVERRIDE_CFG_PVA1WRC,
104 MC_STREAMID_OVERRIDE_CFG_RCER,
105 MC_STREAMID_OVERRIDE_CFG_RCEW,
106 MC_STREAMID_OVERRIDE_CFG_RCEDMAR,
107 MC_STREAMID_OVERRIDE_CFG_RCEDMAW,
108 MC_STREAMID_OVERRIDE_CFG_NVENC1SRD,
109 MC_STREAMID_OVERRIDE_CFG_NVENC1SWR,
110 MC_STREAMID_OVERRIDE_CFG_PCIE0R,
111 MC_STREAMID_OVERRIDE_CFG_PCIE0W,
112 MC_STREAMID_OVERRIDE_CFG_PCIE1R,
113 MC_STREAMID_OVERRIDE_CFG_PCIE1W,
114 MC_STREAMID_OVERRIDE_CFG_PCIE2AR,
115 MC_STREAMID_OVERRIDE_CFG_PCIE2AW,
116 MC_STREAMID_OVERRIDE_CFG_PCIE3R,
117 MC_STREAMID_OVERRIDE_CFG_PCIE3W,
118 MC_STREAMID_OVERRIDE_CFG_PCIE4R,
119 MC_STREAMID_OVERRIDE_CFG_PCIE4W,
120 MC_STREAMID_OVERRIDE_CFG_PCIE5R,
121 MC_STREAMID_OVERRIDE_CFG_PCIE5W,
122 MC_STREAMID_OVERRIDE_CFG_ISPFALW,
123 MC_STREAMID_OVERRIDE_CFG_DLA0RDA1,
124 MC_STREAMID_OVERRIDE_CFG_DLA1RDA1,
125 MC_STREAMID_OVERRIDE_CFG_PVA0RDA1,
126 MC_STREAMID_OVERRIDE_CFG_PVA0RDB1,
127 MC_STREAMID_OVERRIDE_CFG_PVA1RDA1,
128 MC_STREAMID_OVERRIDE_CFG_PVA1RDB1,
129 MC_STREAMID_OVERRIDE_CFG_PCIE5R1,
130 MC_STREAMID_OVERRIDE_CFG_NVENCSRD1,
131 MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1,
132 MC_STREAMID_OVERRIDE_CFG_ISPRA1,
Pritesh Raithathab1914ae2018-03-09 10:15:17 +0530[diff] [blame]133 MC_STREAMID_OVERRIDE_CFG_PCIE0R1,
Varun Wadekar00759902017-05-31 11:41:00 -0700[diff] [blame]134 MC_STREAMID_OVERRIDE_CFG_MIU0R,
135 MC_STREAMID_OVERRIDE_CFG_MIU0W,
136 MC_STREAMID_OVERRIDE_CFG_MIU1R,
137 MC_STREAMID_OVERRIDE_CFG_MIU1W,
138 MC_STREAMID_OVERRIDE_CFG_MIU2R,
139 MC_STREAMID_OVERRIDE_CFG_MIU2W,
140 MC_STREAMID_OVERRIDE_CFG_MIU3R,
Pravinf74639e2018-05-11 15:14:19 +0530[diff] [blame]141 MC_STREAMID_OVERRIDE_CFG_MIU3W,
142 MC_STREAMID_OVERRIDE_CFG_MIU4R,
143 MC_STREAMID_OVERRIDE_CFG_MIU4W,
144 MC_STREAMID_OVERRIDE_CFG_MIU5R,
145 MC_STREAMID_OVERRIDE_CFG_MIU5W
Varun Wadekar00759902017-05-31 11:41:00 -0700[diff] [blame]146};
147
148/*******************************************************************************
149 * Array to hold the security configs for stream IDs
150 ******************************************************************************/
151const static mc_streamid_security_cfg_t tegra194_streamid_sec_cfgs[] = {
Pritesh Raithatha649eb242018-06-06 11:02:55 +0530[diff] [blame]152 mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, DISABLE),
153 mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
154 mc_make_sec_cfg(NVENCSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
155 mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, DISABLE),
156 mc_make_sec_cfg(NVENCSWR, NON_SECURE, NO_OVERRIDE, DISABLE),
157 mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, DISABLE),
158 mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, DISABLE),
Varun Wadekar00759902017-05-31 11:41:00 -0700[diff] [blame]159 mc_make_sec_cfg(ISPRA, NON_SECURE, NO_OVERRIDE, ENABLE),
160 mc_make_sec_cfg(ISPFALR, NON_SECURE, NO_OVERRIDE, ENABLE),
161 mc_make_sec_cfg(ISPWA, NON_SECURE, NO_OVERRIDE, ENABLE),
162 mc_make_sec_cfg(ISPWB, NON_SECURE, NO_OVERRIDE, ENABLE),
Ajay Gupta81621092017-08-01 15:53:04 -0700[diff] [blame]163 mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, NO_OVERRIDE, ENABLE),
164 mc_make_sec_cfg(XUSB_HOSTW, NON_SECURE, NO_OVERRIDE, ENABLE),
165 mc_make_sec_cfg(XUSB_DEVR, NON_SECURE, NO_OVERRIDE, ENABLE),
166 mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, NO_OVERRIDE, ENABLE),
Pritesh Raithatha649eb242018-06-06 11:02:55 +0530[diff] [blame]167 mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
168 mc_make_sec_cfg(TSECSWR, NON_SECURE, NO_OVERRIDE, DISABLE),
169 mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, DISABLE),
170 mc_make_sec_cfg(SDMMCR, NON_SECURE, OVERRIDE, DISABLE),
171 mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, DISABLE),
172 mc_make_sec_cfg(SDMMCWA, NON_SECURE, OVERRIDE, DISABLE),
173 mc_make_sec_cfg(SDMMCW, NON_SECURE, OVERRIDE, DISABLE),
174 mc_make_sec_cfg(SDMMCWAB, NON_SECURE, OVERRIDE, DISABLE),
175 mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
176 mc_make_sec_cfg(VICSWR, NON_SECURE, NO_OVERRIDE, DISABLE),
Varun Wadekar00759902017-05-31 11:41:00 -0700[diff] [blame]177 mc_make_sec_cfg(VIW, NON_SECURE, NO_OVERRIDE, ENABLE),
Pritesh Raithatha649eb242018-06-06 11:02:55 +0530[diff] [blame]178 mc_make_sec_cfg(NVDECSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
179 mc_make_sec_cfg(NVDECSWR, NON_SECURE, NO_OVERRIDE, DISABLE),
180 mc_make_sec_cfg(APER, NON_SECURE, NO_OVERRIDE, DISABLE),
181 mc_make_sec_cfg(APEW, NON_SECURE, NO_OVERRIDE, DISABLE),
182 mc_make_sec_cfg(NVJPGSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
183 mc_make_sec_cfg(NVJPGSWR, NON_SECURE, NO_OVERRIDE, DISABLE),
184 mc_make_sec_cfg(SESRD, NON_SECURE, NO_OVERRIDE, DISABLE),
185 mc_make_sec_cfg(SESWR, NON_SECURE, NO_OVERRIDE, DISABLE),
186 mc_make_sec_cfg(AXIAPR, NON_SECURE, OVERRIDE, DISABLE),
187 mc_make_sec_cfg(AXIAPW, NON_SECURE, OVERRIDE, DISABLE),
188 mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, DISABLE),
189 mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, DISABLE),
190 mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, DISABLE),
191 mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, DISABLE),
Varun Wadekar00759902017-05-31 11:41:00 -0700[diff] [blame]192 mc_make_sec_cfg(AXISR, SECURE, NO_OVERRIDE, DISABLE),
193 mc_make_sec_cfg(AXISW, SECURE, NO_OVERRIDE, DISABLE),
Pritesh Raithatha649eb242018-06-06 11:02:55 +0530[diff] [blame]194 mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, DISABLE),
195 mc_make_sec_cfg(EQOSW, NON_SECURE, OVERRIDE, DISABLE),
196 mc_make_sec_cfg(UFSHCR, NON_SECURE, OVERRIDE, DISABLE),
197 mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, DISABLE),
198 mc_make_sec_cfg(NVDISPLAYR, NON_SECURE, OVERRIDE, DISABLE),
199 mc_make_sec_cfg(BPMPR, NON_SECURE, NO_OVERRIDE, DISABLE),
200 mc_make_sec_cfg(BPMPW, NON_SECURE, NO_OVERRIDE, DISABLE),
201 mc_make_sec_cfg(BPMPDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
202 mc_make_sec_cfg(BPMPDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
203 mc_make_sec_cfg(AONR, NON_SECURE, NO_OVERRIDE, DISABLE),
204 mc_make_sec_cfg(AONW, NON_SECURE, NO_OVERRIDE, DISABLE),
205 mc_make_sec_cfg(AONDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
206 mc_make_sec_cfg(AONDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
207 mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, DISABLE),
208 mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, DISABLE),
209 mc_make_sec_cfg(SCEDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
210 mc_make_sec_cfg(SCEDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
211 mc_make_sec_cfg(APEDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
212 mc_make_sec_cfg(APEDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
213 mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, DISABLE),
214 mc_make_sec_cfg(VICSRD1, NON_SECURE, NO_OVERRIDE, DISABLE),
215 mc_make_sec_cfg(NVDECSRD1, NON_SECURE, NO_OVERRIDE, DISABLE),
Varun Wadekar00759902017-05-31 11:41:00 -0700[diff] [blame]216 mc_make_sec_cfg(VIFALR, NON_SECURE, NO_OVERRIDE, ENABLE),
217 mc_make_sec_cfg(VIFALW, NON_SECURE, NO_OVERRIDE, ENABLE),
Pritesh Raithatha649eb242018-06-06 11:02:55 +0530[diff] [blame]218 mc_make_sec_cfg(DLA0RDA, NON_SECURE, NO_OVERRIDE, DISABLE),
219 mc_make_sec_cfg(DLA0FALRDB, NON_SECURE, NO_OVERRIDE, DISABLE),
220 mc_make_sec_cfg(DLA0WRA, NON_SECURE, NO_OVERRIDE, DISABLE),
221 mc_make_sec_cfg(DLA0FALWRB, NON_SECURE, NO_OVERRIDE, DISABLE),
222 mc_make_sec_cfg(DLA1RDA, NON_SECURE, NO_OVERRIDE, DISABLE),
223 mc_make_sec_cfg(DLA1FALRDB, NON_SECURE, NO_OVERRIDE, DISABLE),
224 mc_make_sec_cfg(DLA1WRA, NON_SECURE, NO_OVERRIDE, DISABLE),
225 mc_make_sec_cfg(DLA1FALWRB, NON_SECURE, NO_OVERRIDE, DISABLE),
226 mc_make_sec_cfg(PVA0RDA, NON_SECURE, NO_OVERRIDE, DISABLE),
227 mc_make_sec_cfg(PVA0RDB, NON_SECURE, NO_OVERRIDE, DISABLE),
228 mc_make_sec_cfg(PVA0RDC, NON_SECURE, NO_OVERRIDE, DISABLE),
229 mc_make_sec_cfg(PVA0WRA, NON_SECURE, NO_OVERRIDE, DISABLE),
230 mc_make_sec_cfg(PVA0WRB, NON_SECURE, NO_OVERRIDE, DISABLE),
231 mc_make_sec_cfg(PVA0WRC, NON_SECURE, NO_OVERRIDE, DISABLE),
232 mc_make_sec_cfg(PVA1RDA, NON_SECURE, NO_OVERRIDE, DISABLE),
233 mc_make_sec_cfg(PVA1RDB, NON_SECURE, NO_OVERRIDE, DISABLE),
234 mc_make_sec_cfg(PVA1RDC, NON_SECURE, NO_OVERRIDE, DISABLE),
235 mc_make_sec_cfg(PVA1WRA, NON_SECURE, NO_OVERRIDE, DISABLE),
236 mc_make_sec_cfg(PVA1WRB, NON_SECURE, NO_OVERRIDE, DISABLE),
237 mc_make_sec_cfg(PVA1WRC, NON_SECURE, NO_OVERRIDE, DISABLE),
238 mc_make_sec_cfg(RCER, NON_SECURE, NO_OVERRIDE, DISABLE),
239 mc_make_sec_cfg(RCEW, NON_SECURE, NO_OVERRIDE, DISABLE),
240 mc_make_sec_cfg(RCEDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
241 mc_make_sec_cfg(RCEDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
242 mc_make_sec_cfg(NVENC1SRD, NON_SECURE, NO_OVERRIDE, DISABLE),
243 mc_make_sec_cfg(NVENC1SWR, NON_SECURE, NO_OVERRIDE, DISABLE),
244 mc_make_sec_cfg(PCIE0R, NON_SECURE, OVERRIDE, DISABLE),
245 mc_make_sec_cfg(PCIE0W, NON_SECURE, OVERRIDE, DISABLE),
246 mc_make_sec_cfg(PCIE1R, NON_SECURE, OVERRIDE, DISABLE),
247 mc_make_sec_cfg(PCIE1W, NON_SECURE, OVERRIDE, DISABLE),
248 mc_make_sec_cfg(PCIE2AR, NON_SECURE, OVERRIDE, DISABLE),
249 mc_make_sec_cfg(PCIE2AW, NON_SECURE, OVERRIDE, DISABLE),
250 mc_make_sec_cfg(PCIE3R, NON_SECURE, OVERRIDE, DISABLE),
251 mc_make_sec_cfg(PCIE3W, NON_SECURE, OVERRIDE, DISABLE),
252 mc_make_sec_cfg(PCIE4R, NON_SECURE, OVERRIDE, DISABLE),
253 mc_make_sec_cfg(PCIE4W, NON_SECURE, OVERRIDE, DISABLE),
254 mc_make_sec_cfg(PCIE5R, NON_SECURE, OVERRIDE, DISABLE),
255 mc_make_sec_cfg(PCIE5W, NON_SECURE, OVERRIDE, DISABLE),
Varun Wadekar00759902017-05-31 11:41:00 -0700[diff] [blame]256 mc_make_sec_cfg(ISPFALW, NON_SECURE, NO_OVERRIDE, ENABLE),
Pritesh Raithatha649eb242018-06-06 11:02:55 +0530[diff] [blame]257 mc_make_sec_cfg(DLA0RDA1, NON_SECURE, NO_OVERRIDE, DISABLE),
258 mc_make_sec_cfg(DLA1RDA1, NON_SECURE, NO_OVERRIDE, DISABLE),
259 mc_make_sec_cfg(PVA0RDA1, NON_SECURE, NO_OVERRIDE, DISABLE),
260 mc_make_sec_cfg(PVA0RDB1, NON_SECURE, NO_OVERRIDE, DISABLE),
261 mc_make_sec_cfg(PVA1RDA1, NON_SECURE, NO_OVERRIDE, DISABLE),
262 mc_make_sec_cfg(PVA1RDB1, NON_SECURE, NO_OVERRIDE, DISABLE),
263 mc_make_sec_cfg(PCIE5R1, NON_SECURE, OVERRIDE, DISABLE),
264 mc_make_sec_cfg(NVENCSRD1, NON_SECURE, NO_OVERRIDE, DISABLE),
265 mc_make_sec_cfg(NVENC1SRD1, NON_SECURE, NO_OVERRIDE, DISABLE),
Varun Wadekar00759902017-05-31 11:41:00 -0700[diff] [blame]266 mc_make_sec_cfg(ISPRA1, NON_SECURE, NO_OVERRIDE, ENABLE),
Pritesh Raithatha649eb242018-06-06 11:02:55 +0530[diff] [blame]267 mc_make_sec_cfg(PCIE0R1, NON_SECURE, OVERRIDE, DISABLE),
268 mc_make_sec_cfg(MIU0R, NON_SECURE, OVERRIDE, DISABLE),
269 mc_make_sec_cfg(MIU0W, NON_SECURE, OVERRIDE, DISABLE),
270 mc_make_sec_cfg(MIU1R, NON_SECURE, OVERRIDE, DISABLE),
271 mc_make_sec_cfg(MIU1W, NON_SECURE, OVERRIDE, DISABLE),
272 mc_make_sec_cfg(MIU2R, NON_SECURE, OVERRIDE, DISABLE),
273 mc_make_sec_cfg(MIU2W, NON_SECURE, OVERRIDE, DISABLE),
274 mc_make_sec_cfg(MIU3R, NON_SECURE, OVERRIDE, DISABLE),
Pravinf74639e2018-05-11 15:14:19 +0530[diff] [blame]275 mc_make_sec_cfg(MIU3W, NON_SECURE, OVERRIDE, DISABLE),
276 mc_make_sec_cfg(MIU4R, NON_SECURE, OVERRIDE, DISABLE),
277 mc_make_sec_cfg(MIU4W, NON_SECURE, OVERRIDE, DISABLE),
278 mc_make_sec_cfg(MIU5R, NON_SECURE, OVERRIDE, DISABLE),
279 mc_make_sec_cfg(MIU5W, NON_SECURE, OVERRIDE, DISABLE)
Varun Wadekar00759902017-05-31 11:41:00 -0700[diff] [blame]280};
281
Varun Wadekar00759902017-05-31 11:41:00 -0700[diff] [blame]282/*******************************************************************************
283 * Struct to hold the memory controller settings
284 ******************************************************************************/
285static tegra_mc_settings_t tegra194_mc_settings = {
286 .streamid_override_cfg = tegra194_streamid_override_regs,
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800[diff] [blame]287 .num_streamid_override_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_override_regs),
Varun Wadekar00759902017-05-31 11:41:00 -0700[diff] [blame]288 .streamid_security_cfg = tegra194_streamid_sec_cfgs,
Stefan Kristiansson1be9a9e2018-04-24 16:02:17 +0300[diff] [blame]289 .num_streamid_security_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_sec_cfgs)
Varun Wadekar00759902017-05-31 11:41:00 -0700[diff] [blame]290};
291
292/*******************************************************************************
293 * Handler to return the pointer to the memory controller's settings struct
294 ******************************************************************************/
295tegra_mc_settings_t *tegra_get_mc_settings(void)
296{
297 return &tegra194_mc_settings;
Steven Kaoee93ed12017-11-14 19:12:58 +0800[diff] [blame]298}
299
300/*******************************************************************************
301 * Handler to program the scratch registers with TZDRAM settings for the
302 * resume firmware
303 ******************************************************************************/
304void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes)
305{
Steven Kaob2b43052017-11-30 11:53:29 +0800[diff] [blame]306 uint32_t sec_reg_ctrl = tegra_mc_read_32(MC_SECURITY_CFG_REG_CTRL_0);
307
Steven Kaoee93ed12017-11-14 19:12:58 +0800[diff] [blame]308 /*
Steven Kaob2b43052017-11-30 11:53:29 +0800[diff] [blame]309 * Check TZDRAM carveout register access status. Setup TZDRAM fence
310 * only if access is enabled.
Steven Kaoee93ed12017-11-14 19:12:58 +0800[diff] [blame]311 */
Steven Kaob2b43052017-11-30 11:53:29 +0800[diff] [blame]312 if ((sec_reg_ctrl & SECURITY_CFG_WRITE_ACCESS_BIT) ==
313 SECURITY_CFG_WRITE_ACCESS_ENABLE) {
Steven Kaoee93ed12017-11-14 19:12:58 +0800[diff] [blame]314
315 /*
316 * Setup the Memory controller to allow only secure accesses to
317 * the TZDRAM carveout
318 */
319 INFO("Configuring TrustZone DRAM Memory Carveout\n");
320
321 tegra_mc_write_32(MC_SECURITY_CFG0_0, (uint32_t)phys_base);
322 tegra_mc_write_32(MC_SECURITY_CFG3_0, (uint32_t)(phys_base >> 32));
323 tegra_mc_write_32(MC_SECURITY_CFG1_0, (uint32_t)(size_in_bytes >> 20));
324
325 /*
326 * MCE propagates the security configuration values across the
327 * CCPLEX.
328 */
329 (void)mce_update_gsc_tzdram();
330 }
331}