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Achin Gupta76717892014-05-09 11:42:56 +01001/*
2 * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch_helpers.h>
32#include <assert.h>
33#include <debug.h>
34#include <gic_v2.h>
Achin Gupta76717892014-05-09 11:42:56 +010035#include <platform.h>
Dan Handleyed6ff952014-05-14 17:44:19 +010036#include <platform_def.h>
Dan Handleye2c27f52014-08-01 17:58:27 +010037#include <tsp.h>
38#include "tsp_private.h"
Achin Gupta76717892014-05-09 11:42:56 +010039
40/*******************************************************************************
41 * This function updates the TSP statistics for FIQs handled synchronously i.e
42 * the ones that have been handed over by the TSPD. It also keeps count of the
43 * number of times control was passed back to the TSPD after handling an FIQ.
44 * In the future it will be possible that the TSPD hands over an FIQ to the TSP
45 * but does not expect it to return execution. This statistic will be useful to
46 * distinguish between these two models of synchronous FIQ handling.
47 * The 'elr_el3' parameter contains the address of the instruction in normal
48 * world where this FIQ was generated.
49 ******************************************************************************/
50void tsp_update_sync_fiq_stats(uint32_t type, uint64_t elr_el3)
51{
52 uint64_t mpidr = read_mpidr();
53 uint32_t linear_id = platform_get_core_pos(mpidr);
54
55 tsp_stats[linear_id].sync_fiq_count++;
56 if (type == TSP_HANDLE_FIQ_AND_RETURN)
57 tsp_stats[linear_id].sync_fiq_ret_count++;
58
Dan Handley91b624e2014-07-29 17:14:00 +010059#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
Achin Gupta76717892014-05-09 11:42:56 +010060 spin_lock(&console_lock);
Dan Handley91b624e2014-07-29 17:14:00 +010061 VERBOSE("TSP: cpu 0x%x sync fiq request from 0x%llx\n",
62 mpidr, elr_el3);
63 VERBOSE("TSP: cpu 0x%x: %d sync fiq requests, %d sync fiq returns\n",
64 mpidr,
65 tsp_stats[linear_id].sync_fiq_count,
66 tsp_stats[linear_id].sync_fiq_ret_count);
Achin Gupta76717892014-05-09 11:42:56 +010067 spin_unlock(&console_lock);
Dan Handley91b624e2014-07-29 17:14:00 +010068#endif
Achin Gupta76717892014-05-09 11:42:56 +010069}
70
71/*******************************************************************************
72 * TSP FIQ handler called as a part of both synchronous and asynchronous
73 * handling of FIQ interrupts. It returns 0 upon successfully handling a S-EL1
74 * FIQ and treats all other FIQs as EL3 interrupts. It assumes that the GIC
75 * architecture version in v2.0 and the secure physical timer interrupt is the
76 * only S-EL1 interrupt that it needs to handle.
77 ******************************************************************************/
Juan Castillo2d552402014-06-13 17:05:10 +010078int32_t tsp_fiq_handler(void)
Achin Gupta76717892014-05-09 11:42:56 +010079{
80 uint64_t mpidr = read_mpidr();
81 uint32_t linear_id = platform_get_core_pos(mpidr), id;
82
83 /*
84 * Get the highest priority pending interrupt id and see if it is the
85 * secure physical generic timer interrupt in which case, handle it.
86 * Otherwise throw this interrupt at the EL3 firmware.
87 */
Dan Handley701fea72014-05-27 16:17:21 +010088 id = plat_ic_get_pending_interrupt_id();
Achin Gupta76717892014-05-09 11:42:56 +010089
90 /* TSP can only handle the secure physical timer interrupt */
Dan Handley4fd2f5c2014-08-04 11:41:20 +010091 if (id != TSP_IRQ_SEC_PHY_TIMER)
Achin Gupta76717892014-05-09 11:42:56 +010092 return TSP_EL3_FIQ;
93
94 /*
95 * Handle the interrupt. Also sanity check if it has been preempted by
96 * another secure interrupt through an assertion.
97 */
Dan Handley701fea72014-05-27 16:17:21 +010098 id = plat_ic_acknowledge_interrupt();
Dan Handley4fd2f5c2014-08-04 11:41:20 +010099 assert(id == TSP_IRQ_SEC_PHY_TIMER);
Achin Gupta76717892014-05-09 11:42:56 +0100100 tsp_generic_timer_handler();
Dan Handley701fea72014-05-27 16:17:21 +0100101 plat_ic_end_of_interrupt(id);
Achin Gupta76717892014-05-09 11:42:56 +0100102
103 /* Update the statistics and print some messages */
104 tsp_stats[linear_id].fiq_count++;
Dan Handley91b624e2014-07-29 17:14:00 +0100105#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
Achin Gupta76717892014-05-09 11:42:56 +0100106 spin_lock(&console_lock);
Dan Handley91b624e2014-07-29 17:14:00 +0100107 VERBOSE("TSP: cpu 0x%x handled fiq %d\n",
Achin Gupta76717892014-05-09 11:42:56 +0100108 mpidr, id);
Dan Handley91b624e2014-07-29 17:14:00 +0100109 VERBOSE("TSP: cpu 0x%x: %d fiq requests\n",
Achin Gupta76717892014-05-09 11:42:56 +0100110 mpidr, tsp_stats[linear_id].fiq_count);
111 spin_unlock(&console_lock);
Dan Handley91b624e2014-07-29 17:14:00 +0100112#endif
Achin Gupta76717892014-05-09 11:42:56 +0100113 return 0;
114}
Soby Mathew9f71f702014-05-09 20:49:17 +0100115
Juan Castillo2d552402014-06-13 17:05:10 +0100116int32_t tsp_irq_received(void)
Soby Mathew9f71f702014-05-09 20:49:17 +0100117{
118 uint64_t mpidr = read_mpidr();
119 uint32_t linear_id = platform_get_core_pos(mpidr);
120
121 tsp_stats[linear_id].irq_count++;
Dan Handley91b624e2014-07-29 17:14:00 +0100122#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
Soby Mathew9f71f702014-05-09 20:49:17 +0100123 spin_lock(&console_lock);
Dan Handley91b624e2014-07-29 17:14:00 +0100124 VERBOSE("TSP: cpu 0x%x received irq\n", mpidr);
125 VERBOSE("TSP: cpu 0x%x: %d irq requests\n",
126 mpidr, tsp_stats[linear_id].irq_count);
Soby Mathew9f71f702014-05-09 20:49:17 +0100127 spin_unlock(&console_lock);
Dan Handley91b624e2014-07-29 17:14:00 +0100128#endif
Soby Mathew9f71f702014-05-09 20:49:17 +0100129 return TSP_PREEMPTED;
130}